From 57ea45a7084fe7220fc1b3dd2b00cdfb87c38eb1 Mon Sep 17 00:00:00 2001 From: Hans Wennborg Date: Thu, 25 Jan 2018 15:28:01 +0000 Subject: Merging r323369 and r323371: ------------------------------------------------------------------------ r323369 | aemerson | 2018-01-24 20:59:29 +0100 (Wed, 24 Jan 2018) | 4 lines [GlobalISel] Don't fall back to FastISel. Apparently checking the pass structure isn't enough to ensure that we don't fall back to FastISel, as it's set up as part of the SelectionDAGISel. ------------------------------------------------------------------------ ------------------------------------------------------------------------ r323371 | aemerson | 2018-01-24 21:35:37 +0100 (Wed, 24 Jan 2018) | 12 lines [AArch64][GlobalISel] Fall back during AArch64 isel if we have a volatile load. The tablegen imported patterns for sext(load(a)) don't check for single uses of the load or delete the original after matching. As a result two loads are left in the generated code. This particular issue will be fixed by adding support for a G_SEXTLOAD opcode in future. There are however other potential issues around this that wouldn't be fixed by a G_SEXTLOAD, so until we have a proper solution we don't try to handle volatile loads at all in the AArch64 selector. Fixes/works around PR36018. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@323434 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/AArch64/GlobalISel/fallback-nofastisel.ll | 10 ++++++++++ .../GlobalISel/irtranslator-volatile-load-pr36018.ll | 14 ++++++++++++++ 2 files changed, 24 insertions(+) create mode 100644 test/CodeGen/AArch64/GlobalISel/fallback-nofastisel.ll create mode 100644 test/CodeGen/AArch64/GlobalISel/irtranslator-volatile-load-pr36018.ll (limited to 'test/CodeGen/AArch64') diff --git a/test/CodeGen/AArch64/GlobalISel/fallback-nofastisel.ll b/test/CodeGen/AArch64/GlobalISel/fallback-nofastisel.ll new file mode 100644 index 00000000000..84d8faf62c8 --- /dev/null +++ b/test/CodeGen/AArch64/GlobalISel/fallback-nofastisel.ll @@ -0,0 +1,10 @@ +; RUN: llc -mtriple=aarch64_be-- %s -o /dev/null -debug-only=isel -O0 2>&1 | FileCheck %s + +; This test uses big endian in order to force an abort since it's not currently supported for GISel. +; The purpose is to check that we don't fall back to FastISel. Checking the pass structure is insufficient +; because the FastISel is set up in the SelectionDAGISel, so it doesn't appear on the pass structure. + +; CHECK-NOT: Enabling fast-ise +define void @empty() { + ret void +} diff --git a/test/CodeGen/AArch64/GlobalISel/irtranslator-volatile-load-pr36018.ll b/test/CodeGen/AArch64/GlobalISel/irtranslator-volatile-load-pr36018.ll new file mode 100644 index 00000000000..9bda39c9fca --- /dev/null +++ b/test/CodeGen/AArch64/GlobalISel/irtranslator-volatile-load-pr36018.ll @@ -0,0 +1,14 @@ +; RUN: llc -O0 -mtriple=aarch64-apple-ios -o - %s | FileCheck %s + +@g = global i16 0, align 2 +declare void @bar(i32) + +; Check that only one load is generated. We fall back to +define hidden void @foo() { +; CHECK-NOT: ldrh +; CHECK: ldrsh + %1 = load volatile i16, i16* @g, align 2 + %2 = sext i16 %1 to i32 + call void @bar(i32 %2) + ret void +} -- cgit v1.2.3