From b546fdde4c1200eed4de7c933403f1fedcf56804 Mon Sep 17 00:00:00 2001 From: Martin Elshuber Date: Wed, 31 Oct 2018 14:39:34 +0100 Subject: [XGeneSched] Fixed multiple InstRW --- lib/Target/AArch64/AArch64SchedXGene.td | 564 ++++++++++++++------------------ 1 file changed, 243 insertions(+), 321 deletions(-) diff --git a/lib/Target/AArch64/AArch64SchedXGene.td b/lib/Target/AArch64/AArch64SchedXGene.td index 772451382f7..ff635748363 100644 --- a/lib/Target/AArch64/AArch64SchedXGene.td +++ b/lib/Target/AArch64/AArch64SchedXGene.td @@ -1090,50 +1090,30 @@ def : InstRW<[XGeneWriteF1Fcvt], (instregex "FCVTZ(S|U)(s|d)$")>; // 1Ld1LdSbfm1SbfmAlu LDPSW (post-indexed) // 1Ld1LdSbfm1SbfmAlu LDPSW (pre-indexed) //--- -def : InstRW<[XGeneWriteLD1Ld], (instregex "LDR(W|X|S|D|Q)l$")>; -def : InstRW<[XGeneWriteLD1Ld], (instregex "LDUR(X|W|HH|BB)i$")>; -def : InstRW<[XGeneWriteLD1Ld], (instregex "LDR(BB|HH|W|X)ro(X|W)$")>; -def : InstRW<[XGeneWriteLD1Ld], (instregex "LDR(BB|HH|W|X|B|H|S|D|Q)ui$")>; - -def : InstRW<[XGeneWriteLD1LdLd], (instregex "LDP(W|X)i$")>; - -def : InstRW<[XGeneWriteLD1LdAlu], (instregex "LDR(BB|HH|W|X)post$")>; -def : InstRW<[XGeneWriteLD1LdAlu], (instregex "LDR(BB|HH|W|X)pre$")>; - -def : InstRW<[XGeneWriteLD1LdLdAlu], (instregex "LDP(W|X)post$")>; -def : InstRW<[XGeneWriteLD1LdLdAlu], (instregex "LDP(W|X)pre$")>; - -def : InstRW<[XGeneWriteLD1Ld1Sbfm], (instregex "LDRSWl$")>; -def : InstRW<[XGeneWriteLD1Ld1Sbfm], (instregex "LDURS(BW|BX|HW|HX|W)i$")>; -def : InstRW<[XGeneWriteLD1Ld1Sbfm], (instregex "LDRS(BW|BX|HW|HX|W)ro(X|W)$")>; -def : InstRW<[XGeneWriteLD1Ld1Sbfm], (instregex "LDRS(BW|BX|HW|HX|W)ui$")>; - -def : InstRW<[XGeneWriteLD1Ld1SbfmAlu], (instregex "LDRS(BW|BX|HW|HX|W)post$")>; -def : InstRW<[XGeneWriteLD1Ld1SbfmAlu], (instregex "LDRS(BW|BX|HW|HX|W)pre$")>; - -def : InstRW<[XGeneWriteLD1Ld1LdSbfm1Sbfm], (instregex "LDPSWi$")>; -def : InstRW<[XGeneWriteLD1Ld1LdSbfm1SbfmAlu], (instregex "LDPSWpost$")>; -def : InstRW<[XGeneWriteLD1Ld1LdSbfm1SbfmAlu], (instregex "LDPSWpre$")>; - -// For read advance - all integer load ops -def : InstRW<[XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDR(W|X|S|D|Q)l$")>; -def : InstRW<[XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDUR(X|W|HH|BB)i$")>; -def : InstRW<[XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDR(BB|HH|W|X)ro(X|W)$")>; -def : InstRW<[XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDR(BB|HH|W|X|B|H|S|D|Q)ui$")>; -def : InstRW<[XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDP(W|X)i$")>; -def : InstRW<[XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDR(BB|HH|W|X)post$")>; -def : InstRW<[XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDR(BB|HH|W|X)pre$")>; -def : InstRW<[XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDP(W|X)post$")>; -def : InstRW<[XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDP(W|X)pre$")>; -def : InstRW<[XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDRSWl$")>; -def : InstRW<[XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDURS(BW|BX|HW|HX|W)i$")>; -def : InstRW<[XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDRS(BW|BX|HW|HX|W)ro(X|W)$")>; -def : InstRW<[XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDRS(BW|BX|HW|HX|W)ui$")>; -def : InstRW<[XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDRS(BW|BX|HW|HX|W)post$")>; -def : InstRW<[XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDRS(BW|BX|HW|HX|W)pre$")>; -def : InstRW<[XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDPSWi$")>; -def : InstRW<[XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDPSWpost$")>; -def : InstRW<[XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDPSWpre$")>; +def : InstRW<[XGeneWriteLD1Ld, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDR(W|X|S|D|Q)l$")>; +def : InstRW<[XGeneWriteLD1Ld, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDUR(X|W|HH|BB)i$")>; +def : InstRW<[XGeneWriteLD1Ld, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDR(BB|HH|W|X)ro(X|W)$")>; +def : InstRW<[XGeneWriteLD1Ld, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDR(BB|HH|W|X|B|H|S|D|Q)ui$")>; + +def : InstRW<[XGeneWriteLD1LdLd, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDP(W|X)i$")>; + +def : InstRW<[XGeneWriteLD1LdAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDR(BB|HH|W|X)post$")>; +def : InstRW<[XGeneWriteLD1LdAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDR(BB|HH|W|X)pre$")>; + +def : InstRW<[XGeneWriteLD1LdLdAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDP(W|X)post$")>; +def : InstRW<[XGeneWriteLD1LdLdAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDP(W|X)pre$")>; + +def : InstRW<[XGeneWriteLD1Ld1Sbfm, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDRSWl$")>; +def : InstRW<[XGeneWriteLD1Ld1Sbfm, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDURS(BW|BX|HW|HX|W)i$")>; +def : InstRW<[XGeneWriteLD1Ld1Sbfm, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDRS(BW|BX|HW|HX|W)ro(X|W)$")>; +def : InstRW<[XGeneWriteLD1Ld1Sbfm, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDRS(BW|BX|HW|HX|W)ui$")>; + +def : InstRW<[XGeneWriteLD1Ld1SbfmAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDRS(BW|BX|HW|HX|W)post$")>; +def : InstRW<[XGeneWriteLD1Ld1SbfmAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDRS(BW|BX|HW|HX|W)pre$")>; + +def : InstRW<[XGeneWriteLD1Ld1LdSbfm1Sbfm, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDPSWi$")>; +def : InstRW<[XGeneWriteLD1Ld1LdSbfm1SbfmAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDPSWpost$")>; +def : InstRW<[XGeneWriteLD1Ld1LdSbfm1SbfmAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDPSWpre$")>; //--- // Load instructions - 64-bit FP/SIMD (8 groups in total) @@ -1145,13 +1125,13 @@ def : InstRW<[XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDPSWpre$")>; // 1LfLfAlu: LDP (post-indexed, pre-indexed) //--- // for LDUR, the llvm arm64 model only defines the unscaled immediates -def : InstRW<[XGeneWriteLD1Lf], (instregex "LDUR(B|H|S|D)i$")>; -def : InstRW<[XGeneWriteLD1LfAlu], (instregex "LDR(B|H|S|D)post$")>; -def : InstRW<[XGeneWriteLD1LfAlu], (instregex "LDR(B|H|S|D)pre$")>; -def : InstRW<[XGeneWriteLD1LfAlu], (instregex "LDR(B|H|S|D)ro(X|W)$")>; -def : InstRW<[XGeneWriteLD1LfLf], (instregex "LDP(D|S)i$")>; -def : InstRW<[XGeneWriteLD1LfLfAlu], (instregex "LDP(D|S)post$")>; -def : InstRW<[XGeneWriteLD1LfLfAlu], (instregex "LDP(D|S)pre$")>; +def : InstRW<[XGeneWriteLD1Lf, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDUR(B|H|S|D)i$")>; +def : InstRW<[XGeneWriteLD1LfAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDR(B|H|S|D)post$")>; +def : InstRW<[XGeneWriteLD1LfAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDR(B|H|S|D)pre$")>; +def : InstRW<[XGeneWriteLD1LfAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDR(B|H|S|D)ro(X|W)$")>; +def : InstRW<[XGeneWriteLD1LfLf, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDP(D|S)i$")>; +def : InstRW<[XGeneWriteLD1LfLfAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDP(D|S)post$")>; +def : InstRW<[XGeneWriteLD1LfLfAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDP(D|S)pre$")>; //--- // Load instructions - 128-bit FP/SIMD (8 groups in total) @@ -1163,22 +1143,13 @@ def : InstRW<[XGeneWriteLD1LfLfAlu], (instregex "LDP(D|S)pre$")>; // 1LfLfAlu1LfLfAlu: LDP (post-indexed, pre-indexed) //--- // for LDUR, the llvm arm64 model only defines the unscaled immediates -def : InstRW<[XGeneWriteLD1LfLf], (instregex "LDURQi$")>; -def : InstRW<[XGeneWriteLD1LfLfAlu], (instregex "LDRQpost$")>; -def : InstRW<[XGeneWriteLD1LfLfAlu], (instregex "LDRQpre$")>; -def : InstRW<[XGeneWriteLD1LfAlu1Lf], (instregex "LDRQro(X|W)$")>; -def : InstRW<[XGeneWriteLD1LfLfAlu1LfLf], (instregex "LDPQi$")>; -def : InstRW<[XGeneWriteLD1LfLfAlu1LfLfAlu], (instregex "LDPQpost$")>; -def : InstRW<[XGeneWriteLD1LfLfAlu1LfLfAlu], (instregex "LDPQpre$")>; - -// For read advance - all float load ops -def : InstRW<[XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDUR(B|H|S|D|Q)i$")>; -def : InstRW<[XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDR(B|H|S|D|Q)post$")>; -def : InstRW<[XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDR(B|H|S|D|Q)pre$")>; -def : InstRW<[XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDR(B|H|S|D|Q)ro(X|W)$")>; -def : InstRW<[XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDP(D|S|Q)i$")>; -def : InstRW<[XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDP(D|S|Q)post$")>; -def : InstRW<[XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDP(D|S|Q)pre$")>; +def : InstRW<[XGeneWriteLD1LfLf, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDURQi$")>; +def : InstRW<[XGeneWriteLD1LfLfAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDRQpost$")>; +def : InstRW<[XGeneWriteLD1LfLfAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDRQpre$")>; +def : InstRW<[XGeneWriteLD1LfAlu1Lf, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDRQro(X|W)$")>; +def : InstRW<[XGeneWriteLD1LfLfAlu1LfLf, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDPQi$")>; +def : InstRW<[XGeneWriteLD1LfLfAlu1LfLfAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDPQpost$")>; +def : InstRW<[XGeneWriteLD1LfLfAlu1LfLfAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDPQpre$")>; //--- // Vector Load (66 groups in total) @@ -1249,103 +1220,100 @@ def : InstRW<[XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LDP(D|S|Q)pre$")>; // 1X4Lf1X4Asi: LD4 (four registers) // 1X4LfAlu1X4Asi: LD4 (four registers pre/post indexed) //--- -def : InstRW<[XGeneWriteLD1Lc], (instregex "LD1Onev(2s|4h|8b)$")>; -def : InstRW<[XGeneWriteLD1LcAlu], (instregex "LD1Onev(2s|4h|8b)_POST$")>; - -def : InstRW<[XGeneWriteLD1LcLc], (instregex "LD1Onev(4s|8h|16b)$")>; -def : InstRW<[XGeneWriteLD1LcLc], (instregex "LD1Twov(2s|4h|8b)$")>; -def : InstRW<[XGeneWriteLD1LcLc], (instregex "LD2Twov(2s|4h|8b)$")>; -def : InstRW<[XGeneWriteLD1LcLcAlu], (instregex "LD1Onev(4s|8h|16b)_POST$")>; -def : InstRW<[XGeneWriteLD1LcLcAlu], (instregex "LD1Twov(2s|4h|8b)_POST$")>; -def : InstRW<[XGeneWriteLD1LcLcAlu], (instregex "LD2Twov(2s|4h|8b)_POST$")>; - -def : InstRW<[XGeneWriteLD1X3Lc], (instregex "LD1Threev(2s|4h|8b)$")>; -def : InstRW<[XGeneWriteLD1X3Lc], (instregex "LD3Threev(2s|4h|8b)$")>; -def : InstRW<[XGeneWriteLD1X3LcAlu], (instregex "LD1Threev(2s|4h|8b)_POST$")>; -def : InstRW<[XGeneWriteLD1X3LcAlu], (instregex "LD3Threev(2s|4h|8b)_POST$")>; - -def : InstRW<[XGeneWriteLD1X4Lc], (instregex "LD1Twov(4s|8h|16b)$")>; -def : InstRW<[XGeneWriteLD1X4Lc], (instregex "LD1Fourv(2s|4h|8b)$")>; -def : InstRW<[XGeneWriteLD1X4Lc], (instregex "LD2Twov(4s|8h|16b)$")>; -def : InstRW<[XGeneWriteLD1X4Lc], (instregex "LD4Fourv(2s|4h|8b)$")>; -def : InstRW<[XGeneWriteLD1X4LcAlu], (instregex "LD1Twov(4s|8h|16b)_POST$")>; -def : InstRW<[XGeneWriteLD1X4LcAlu], (instregex "LD1Fourv(2s|4h|8b)_POST$")>; -def : InstRW<[XGeneWriteLD1X4LcAlu], (instregex "LD2Twov(4s|8h|16b)_POST$")>; -def : InstRW<[XGeneWriteLD1X4LcAlu], (instregex "LD4Fourv(2s|4h|8b)_POST$")>; - -def : InstRW<[XGeneWriteLD1X6Lc], (instregex "LD1Threev(4s|8h|16b)$")>; -def : InstRW<[XGeneWriteLD1X6Lc], (instregex "LD3Threev(4s|8h|16b)$")>; -def : InstRW<[XGeneWriteLD1X6LcAlu], (instregex "LD1Threev(4s|8h|16b)_POST$")>; -def : InstRW<[XGeneWriteLD1X6LcAlu], (instregex "LD3Threev(4s|8h|16b)_POST$")>; - -def : InstRW<[XGeneWriteLD1X8Lc], (instregex "LD1Fourv(4s|8h|16b)$")>; -def : InstRW<[XGeneWriteLD1X8Lc], (instregex "LD4Fourv(4s|8h|16b)$")>; -def : InstRW<[XGeneWriteLD1X8LcAlu], (instregex "LD1Fourv(4s|8h|16b)_POST$")>; -def : InstRW<[XGeneWriteLD1X8LcAlu], (instregex "LD4Fourv(4s|8h|16b)_POST$")>; - -def : InstRW<[XGeneWriteLD1Lf], (instregex "LD1Onev1d$")>; -def : InstRW<[XGeneWriteLD1Lf], (instregex "LD1Rv(2s|4h|8b)$")>; -def : InstRW<[XGeneWriteLD1Lf], (instregex "LD1Rv(4s|8h|16b)$")>; -def : InstRW<[XGeneWriteLD1Lf], (instregex "LD1Rv(1d|2d)$")>; -def : InstRW<[XGeneWriteLD1LfAlu], (instregex "LD1Onev1d_POST$")>; -def : InstRW<[XGeneWriteLD1LfAlu], (instregex "LD1Rv(2s|4h|8b)_POST$")>; -def : InstRW<[XGeneWriteLD1LfAlu], (instregex "LD1Rv(4s|8h|16b)_POST$")>; -def : InstRW<[XGeneWriteLD1LfAlu], (instregex "LD1Rv(1d|2d)_POST$")>; - -def : InstRW<[XGeneWriteLD1LfLf], (instregex "LD1Onev2d$")>; -def : InstRW<[XGeneWriteLD1LfLf], (instregex "LD1Twov1d$")>; -def : InstRW<[XGeneWriteLD1LfLf], (instregex "LD2Rv(2s|4h|8b)$")>; -def : InstRW<[XGeneWriteLD1LfLf], (instregex "LD2Rv(4s|8h|16b)$")>; -def : InstRW<[XGeneWriteLD1LfLf], (instregex "LD2Rv(1d|2d)$")>; -def : InstRW<[XGeneWriteLD1LfLfAlu], (instregex "LD1Onev2d_POST$")>; -def : InstRW<[XGeneWriteLD1LfLfAlu], (instregex "LD1Twov1d_POST$")>; -def : InstRW<[XGeneWriteLD1LfLfAlu], (instregex "LD2Rv(2s|4h|8b)_POST$")>; -def : InstRW<[XGeneWriteLD1LfLfAlu], (instregex "LD2Rv(4s|8h|16b)_POST$")>; -def : InstRW<[XGeneWriteLD1LfLfAlu], (instregex "LD2Rv(1d|2d)_POST$")>; - -def : InstRW<[XGeneWriteLD1X3Lf], (instregex "LD1Threev1d$")>; -def : InstRW<[XGeneWriteLD1X3Lf], (instregex "LD3Rv(2s|4h|8b)$")>; -def : InstRW<[XGeneWriteLD1X3Lf], (instregex "LD3Rv(4s|8h|16b)$")>; -def : InstRW<[XGeneWriteLD1X3Lf], (instregex "LD3Rv(1d|2d)$")>; -def : InstRW<[XGeneWriteLD1X3LfAlu], (instregex "LD1Threev1d_POST$")>; -def : InstRW<[XGeneWriteLD1X3LfAlu], (instregex "LD3Rv(2s|4h|8b)_POST$")>; -def : InstRW<[XGeneWriteLD1X3LfAlu], (instregex "LD3Rv(4s|8h|16b)_POST$")>; -def : InstRW<[XGeneWriteLD1X3LfAlu], (instregex "LD3Rv(1d|2d)_POST$")>; - -def : InstRW<[XGeneWriteLD1X4Lf], (instregex "LD1Twov2d$")>; -def : InstRW<[XGeneWriteLD1X4Lf], (instregex "LD1Fourv1d$")>; -def : InstRW<[XGeneWriteLD1X4Lf], (instregex "LD2Twov2d$")>; -def : InstRW<[XGeneWriteLD1X4Lf], (instregex "LD4Rv(2s|4h|8b)$")>; -def : InstRW<[XGeneWriteLD1X4Lf], (instregex "LD4Rv(4s|8h|16b)$")>; -def : InstRW<[XGeneWriteLD1X4Lf], (instregex "LD4Rv(1d|2d)$")>; -def : InstRW<[XGeneWriteLD1X4LfAlu], (instregex "LD1Twov2d_POST$")>; -def : InstRW<[XGeneWriteLD1X4LfAlu], (instregex "LD1Fourv1d_POST$")>; -def : InstRW<[XGeneWriteLD1X4LfAlu], (instregex "LD2Twov2d_POST$")>; -def : InstRW<[XGeneWriteLD1X4LfAlu], (instregex "LD4Rv(2s|4h|8b)_POST$")>; -def : InstRW<[XGeneWriteLD1X4LfAlu], (instregex "LD4Rv(4s|8h|16b)_POST$")>; -def : InstRW<[XGeneWriteLD1X4LfAlu], (instregex "LD4Rv(1d|2d)_POST$")>; - -def : InstRW<[XGeneWriteLD1X6Lf], (instregex "LD1Threev2d$")>; -def : InstRW<[XGeneWriteLD1X6Lf], (instregex "LD3Threev2d$")>; -def : InstRW<[XGeneWriteLD1X6LfAlu], (instregex "LD1Threev2d_POST$")>; -def : InstRW<[XGeneWriteLD1X6LfAlu], (instregex "LD3Threev2d_POST$")>; - -def : InstRW<[XGeneWriteLD1X8Lf], (instregex "LD1Fourv2d$")>; -def : InstRW<[XGeneWriteLD1X8Lf], (instregex "LD4Fourv2d$")>; -def : InstRW<[XGeneWriteLD1X8LfAlu], (instregex "LD1Fourv2d_POST$")>; -def : InstRW<[XGeneWriteLD1X8LfAlu], (instregex "LD4Fourv2d_POST$")>; - -def : InstRW<[XGeneWriteLD1Lf1Asi], (instregex "LD1(i8|i16|i32|i64)$")>; -def : InstRW<[XGeneWriteLD1LfAlu1Asi], (instregex "LD1(i8|i16|i32|i64)_POST$")>; -def : InstRW<[XGeneWriteLD1LfLf1AsiAsi], (instregex "LD2(i8|i16|i32|i64)$")>; -def : InstRW<[XGeneWriteLD1LfLfAlu1AsiAsi], (instregex "LD2(i8|i16|i32|i64)_POST$")>; -def : InstRW<[XGeneWriteLD1X3Lf1X3Asi], (instregex "LD3(i8|i16|i32|i64)$")>; -def : InstRW<[XGeneWriteLD1X3LfAlu1X3Asi], (instregex "LD3(i8|i16|i32|i64)_POST$")>; -def : InstRW<[XGeneWriteLD1X4Lf1X4Asi], (instregex "LD4(i8|i16|i32|i64)$")>; -def : InstRW<[XGeneWriteLD1X4LfAlu1X4Asi], (instregex "LD4(i8|i16|i32|i64)_POST$")>; - -//All vector loads for Read Advance -def : InstRW<[XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD(1|2|3|4).*$")>; +def : InstRW<[XGeneWriteLD1Lc, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Onev(2s|4h|8b)$")>; +def : InstRW<[XGeneWriteLD1LcAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Onev(2s|4h|8b)_POST$")>; + +def : InstRW<[XGeneWriteLD1LcLc, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Onev(4s|8h|16b)$")>; +def : InstRW<[XGeneWriteLD1LcLc, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Twov(2s|4h|8b)$")>; +def : InstRW<[XGeneWriteLD1LcLc, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD2Twov(2s|4h|8b)$")>; +def : InstRW<[XGeneWriteLD1LcLcAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Onev(4s|8h|16b)_POST$")>; +def : InstRW<[XGeneWriteLD1LcLcAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Twov(2s|4h|8b)_POST$")>; +def : InstRW<[XGeneWriteLD1LcLcAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD2Twov(2s|4h|8b)_POST$")>; + +def : InstRW<[XGeneWriteLD1X3Lc, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Threev(2s|4h|8b)$")>; +def : InstRW<[XGeneWriteLD1X3Lc, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD3Threev(2s|4h|8b)$")>; +def : InstRW<[XGeneWriteLD1X3LcAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Threev(2s|4h|8b)_POST$")>; +def : InstRW<[XGeneWriteLD1X3LcAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD3Threev(2s|4h|8b)_POST$")>; + +def : InstRW<[XGeneWriteLD1X4Lc, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Twov(4s|8h|16b)$")>; +def : InstRW<[XGeneWriteLD1X4Lc, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Fourv(2s|4h|8b)$")>; +def : InstRW<[XGeneWriteLD1X4Lc, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD2Twov(4s|8h|16b)$")>; +def : InstRW<[XGeneWriteLD1X4Lc, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD4Fourv(2s|4h|8b)$")>; +def : InstRW<[XGeneWriteLD1X4LcAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Twov(4s|8h|16b)_POST$")>; +def : InstRW<[XGeneWriteLD1X4LcAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Fourv(2s|4h|8b)_POST$")>; +def : InstRW<[XGeneWriteLD1X4LcAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD2Twov(4s|8h|16b)_POST$")>; +def : InstRW<[XGeneWriteLD1X4LcAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD4Fourv(2s|4h|8b)_POST$")>; + +def : InstRW<[XGeneWriteLD1X6Lc, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Threev(4s|8h|16b)$")>; +def : InstRW<[XGeneWriteLD1X6Lc, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD3Threev(4s|8h|16b)$")>; +def : InstRW<[XGeneWriteLD1X6LcAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Threev(4s|8h|16b)_POST$")>; +def : InstRW<[XGeneWriteLD1X6LcAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD3Threev(4s|8h|16b)_POST$")>; + +def : InstRW<[XGeneWriteLD1X8Lc, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Fourv(4s|8h|16b)$")>; +def : InstRW<[XGeneWriteLD1X8Lc, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD4Fourv(4s|8h|16b)$")>; +def : InstRW<[XGeneWriteLD1X8LcAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Fourv(4s|8h|16b)_POST$")>; +def : InstRW<[XGeneWriteLD1X8LcAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD4Fourv(4s|8h|16b)_POST$")>; + +def : InstRW<[XGeneWriteLD1Lf, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Onev1d$")>; +def : InstRW<[XGeneWriteLD1Lf, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Rv(2s|4h|8b)$")>; +def : InstRW<[XGeneWriteLD1Lf, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Rv(4s|8h|16b)$")>; +def : InstRW<[XGeneWriteLD1Lf, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Rv(1d|2d)$")>; +def : InstRW<[XGeneWriteLD1LfAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Onev1d_POST$")>; +def : InstRW<[XGeneWriteLD1LfAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Rv(2s|4h|8b)_POST$")>; +def : InstRW<[XGeneWriteLD1LfAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Rv(4s|8h|16b)_POST$")>; +def : InstRW<[XGeneWriteLD1LfAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Rv(1d|2d)_POST$")>; + +def : InstRW<[XGeneWriteLD1LfLf, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Onev2d$")>; +def : InstRW<[XGeneWriteLD1LfLf, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Twov1d$")>; +def : InstRW<[XGeneWriteLD1LfLf, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD2Rv(2s|4h|8b)$")>; +def : InstRW<[XGeneWriteLD1LfLf, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD2Rv(4s|8h|16b)$")>; +def : InstRW<[XGeneWriteLD1LfLf, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD2Rv(1d|2d)$")>; +def : InstRW<[XGeneWriteLD1LfLfAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Onev2d_POST$")>; +def : InstRW<[XGeneWriteLD1LfLfAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Twov1d_POST$")>; +def : InstRW<[XGeneWriteLD1LfLfAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD2Rv(2s|4h|8b)_POST$")>; +def : InstRW<[XGeneWriteLD1LfLfAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD2Rv(4s|8h|16b)_POST$")>; +def : InstRW<[XGeneWriteLD1LfLfAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD2Rv(1d|2d)_POST$")>; + +def : InstRW<[XGeneWriteLD1X3Lf, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Threev1d$")>; +def : InstRW<[XGeneWriteLD1X3Lf, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD3Rv(2s|4h|8b)$")>; +def : InstRW<[XGeneWriteLD1X3Lf, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD3Rv(4s|8h|16b)$")>; +def : InstRW<[XGeneWriteLD1X3Lf, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD3Rv(1d|2d)$")>; +def : InstRW<[XGeneWriteLD1X3LfAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Threev1d_POST$")>; +def : InstRW<[XGeneWriteLD1X3LfAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD3Rv(2s|4h|8b)_POST$")>; +def : InstRW<[XGeneWriteLD1X3LfAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD3Rv(4s|8h|16b)_POST$")>; +def : InstRW<[XGeneWriteLD1X3LfAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD3Rv(1d|2d)_POST$")>; + +def : InstRW<[XGeneWriteLD1X4Lf, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Twov2d$")>; +def : InstRW<[XGeneWriteLD1X4Lf, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Fourv1d$")>; +def : InstRW<[XGeneWriteLD1X4Lf, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD2Twov2d$")>; +def : InstRW<[XGeneWriteLD1X4Lf, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD4Rv(2s|4h|8b)$")>; +def : InstRW<[XGeneWriteLD1X4Lf, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD4Rv(4s|8h|16b)$")>; +def : InstRW<[XGeneWriteLD1X4Lf, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD4Rv(1d|2d)$")>; +def : InstRW<[XGeneWriteLD1X4LfAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Twov2d_POST$")>; +def : InstRW<[XGeneWriteLD1X4LfAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Fourv1d_POST$")>; +def : InstRW<[XGeneWriteLD1X4LfAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD2Twov2d_POST$")>; +def : InstRW<[XGeneWriteLD1X4LfAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD4Rv(2s|4h|8b)_POST$")>; +def : InstRW<[XGeneWriteLD1X4LfAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD4Rv(4s|8h|16b)_POST$")>; +def : InstRW<[XGeneWriteLD1X4LfAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD4Rv(1d|2d)_POST$")>; + +def : InstRW<[XGeneWriteLD1X6Lf, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Threev2d$")>; +def : InstRW<[XGeneWriteLD1X6Lf, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD3Threev2d$")>; +def : InstRW<[XGeneWriteLD1X6LfAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Threev2d_POST$")>; +def : InstRW<[XGeneWriteLD1X6LfAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD3Threev2d_POST$")>; + +def : InstRW<[XGeneWriteLD1X8Lf, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Fourv2d$")>; +def : InstRW<[XGeneWriteLD1X8Lf, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD4Fourv2d$")>; +def : InstRW<[XGeneWriteLD1X8LfAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1Fourv2d_POST$")>; +def : InstRW<[XGeneWriteLD1X8LfAlu, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD4Fourv2d_POST$")>; + +def : InstRW<[XGeneWriteLD1Lf1Asi, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1(i8|i16|i32|i64)$")>; +def : InstRW<[XGeneWriteLD1LfAlu1Asi, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD1(i8|i16|i32|i64)_POST$")>; +def : InstRW<[XGeneWriteLD1LfLf1AsiAsi, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD2(i8|i16|i32|i64)$")>; +def : InstRW<[XGeneWriteLD1LfLfAlu1AsiAsi, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD2(i8|i16|i32|i64)_POST$")>; +def : InstRW<[XGeneWriteLD1X3Lf1X3Asi, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD3(i8|i16|i32|i64)$")>; +def : InstRW<[XGeneWriteLD1X3LfAlu1X3Asi, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD3(i8|i16|i32|i64)_POST$")>; +def : InstRW<[XGeneWriteLD1X4Lf1X4Asi, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD4(i8|i16|i32|i64)$")>; +def : InstRW<[XGeneWriteLD1X4LfAlu1X4Asi, XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD4(i8|i16|i32|i64)_POST$")>; //--- // Store instructions (18 groups in total) @@ -1358,27 +1326,17 @@ def : InstRW<[XGeneReadLDSTI, XGeneReadLDSTF], (instregex "LD(1|2|3|4).*$")>; // 1StStAlu: STP (post-indexed) // 1StStAlu: STP (pre-indexed) //--- -def : InstRW<[XGeneWriteST1St], (instregex "STUR(BB|HH|W|X)i$")>; -def : InstRW<[XGeneWriteST1St], (instregex "STR(BB|HH|W|X)ro(W|X)$")>; -def : InstRW<[XGeneWriteST1St], (instregex "STR(X|W|HH|BB)ui$")>; - -def : InstRW<[XGeneWriteST1StAlu], (instregex "STR(W|X|BB|HH)post$")>; -def : InstRW<[XGeneWriteST1StAlu], (instregex "STR(W|X|BB|HH)pre$")>; +def : InstRW<[XGeneWriteST1St, XGeneWriteSTI], (instregex "STUR(BB|HH|W|X)i$")>; +def : InstRW<[XGeneWriteST1St, XGeneWriteSTI], (instregex "STR(BB|HH|W|X)ro(W|X)$")>; +def : InstRW<[XGeneWriteST1St, XGeneWriteSTI], (instregex "STR(X|W|HH|BB)ui$")>; -def : InstRW<[XGeneWriteST1StSt], (instregex "STP(W|X)i$")>; +def : InstRW<[XGeneWriteST1StAlu, XGeneWriteSTI], (instregex "STR(W|X|BB|HH)post$")>; +def : InstRW<[XGeneWriteST1StAlu, XGeneWriteSTI], (instregex "STR(W|X|BB|HH)pre$")>; -def : InstRW<[XGeneWriteST1StStAlu], (instregex "STP(W|X)post$")>; -def : InstRW<[XGeneWriteST1StStAlu], (instregex "STP(W|X)pre$")>; +def : InstRW<[XGeneWriteST1StSt, XGeneWriteSTI], (instregex "STP(W|X)i$")>; -// Scalar int stores for Read Advance -def : InstRW<[XGeneWriteSTI], (instregex "STUR(BB|HH|W|X)i$")>; -def : InstRW<[XGeneWriteSTI], (instregex "STR(BB|HH|W|X)ro(W|X)$")>; -def : InstRW<[XGeneWriteSTI], (instregex "STR(X|W|HH|BB)ui$")>; -def : InstRW<[XGeneWriteSTI], (instregex "STR(W|X|BB|HH)post$")>; -def : InstRW<[XGeneWriteSTI], (instregex "STR(W|X|BB|HH)pre$")>; -def : InstRW<[XGeneWriteSTI], (instregex "STP(W|X)i$")>; -def : InstRW<[XGeneWriteSTI], (instregex "STP(W|X)post$")>; -def : InstRW<[XGeneWriteSTI], (instregex "STP(W|X)pre$")>; +def : InstRW<[XGeneWriteST1StStAlu, XGeneWriteSTI], (instregex "STP(W|X)post$")>; +def : InstRW<[XGeneWriteST1StStAlu, XGeneWriteSTI], (instregex "STP(W|X)pre$")>; //--- // Store instructions - 64-bit FP/SIMD (8 groups in total) @@ -1390,13 +1348,13 @@ def : InstRW<[XGeneWriteSTI], (instregex "STP(W|X)pre$")>; // 1SfSfAlu: STP (post-indexed, pre-indexed) //--- // for STUR, the llvm arm64 model only defines the unscaled immediates -def : InstRW<[XGeneWriteST1Sf], (instregex "STUR(B|H|S|D)i$")>; -def : InstRW<[XGeneWriteST1SfAlu], (instregex "STR(B|H|S|D)post$")>; -def : InstRW<[XGeneWriteST1SfAlu], (instregex "STR(B|H|S|D)pre$")>; -def : InstRW<[XGeneWriteST1SfAlu], (instregex "STR(B|H|S|D)ro(X|W)$")>; -def : InstRW<[XGeneWriteST1SfSf], (instregex "STP(D|S)i$")>; -def : InstRW<[XGeneWriteST1SfSfAlu], (instregex "STP(D|S)post$")>; -def : InstRW<[XGeneWriteST1SfSfAlu], (instregex "STP(D|S)pre$")>; +def : InstRW<[XGeneWriteST1Sf, XGeneWriteSTF], (instregex "STUR(B|H|S|D)i$")>; +def : InstRW<[XGeneWriteST1SfAlu, XGeneWriteSTF], (instregex "STR(B|H|S|D)post$")>; +def : InstRW<[XGeneWriteST1SfAlu, XGeneWriteSTF], (instregex "STR(B|H|S|D)pre$")>; +def : InstRW<[XGeneWriteST1SfAlu, XGeneWriteSTF], (instregex "STR(B|H|S|D)ro(X|W)$")>; +def : InstRW<[XGeneWriteST1SfSf, XGeneWriteSTF], (instregex "STP(D|S)i$")>; +def : InstRW<[XGeneWriteST1SfSfAlu, XGeneWriteSTF], (instregex "STP(D|S)post$")>; +def : InstRW<[XGeneWriteST1SfSfAlu, XGeneWriteSTF], (instregex "STP(D|S)pre$")>; //--- // Store instructions - 128-bit FP/SIMD (8 groups in total) @@ -1408,22 +1366,13 @@ def : InstRW<[XGeneWriteST1SfSfAlu], (instregex "STP(D|S)pre$")>; // 1SfSfAlu1SfSfAlu: STP (post-indexed, pre-indexed) //--- // for STUR, the llvm arm64 model only defines the unscaled immediates -def : InstRW<[XGeneWriteST1SfSf], (instregex "STURQi$")>; -def : InstRW<[XGeneWriteST1SfSfAlu], (instregex "STRQpost$")>; -def : InstRW<[XGeneWriteST1SfSfAlu], (instregex "STRQpre$")>; -def : InstRW<[XGeneWriteST1SfAlu1Sf], (instregex "STRQro(X|W)$")>; -def : InstRW<[XGeneWriteST1SfSfAlu1SfSf], (instregex "STPQi$")>; -def : InstRW<[XGeneWriteST1SfSfAlu1SfSfAlu], (instregex "STPQpost$")>; -def : InstRW<[XGeneWriteST1SfSfAlu1SfSfAlu], (instregex "STPQpre$")>; - -// Scalar float stores for Read Advance -def : InstRW<[XGeneWriteSTF], (instregex "STUR(B|H|S|D|Q)i$")>; -def : InstRW<[XGeneWriteSTF], (instregex "STR(B|H|S|D|Q)post$")>; -def : InstRW<[XGeneWriteSTF], (instregex "STR(B|H|S|D|Q)pre$")>; -def : InstRW<[XGeneWriteSTF], (instregex "STR(B|H|S|D|Q)ro(X|W)$")>; -def : InstRW<[XGeneWriteSTF], (instregex "STP(D|S|Q)i$")>; -def : InstRW<[XGeneWriteSTF], (instregex "STP(D|S|Q)post$")>; -def : InstRW<[XGeneWriteSTF], (instregex "STP(D|S|Q)pre$")>; +def : InstRW<[XGeneWriteST1SfSf, XGeneWriteSTF], (instregex "STURQi$")>; +def : InstRW<[XGeneWriteST1SfSfAlu, XGeneWriteSTF], (instregex "STRQpost$")>; +def : InstRW<[XGeneWriteST1SfSfAlu, XGeneWriteSTF], (instregex "STRQpre$")>; +def : InstRW<[XGeneWriteST1SfAlu1Sf, XGeneWriteSTF], (instregex "STRQro(X|W)$")>; +def : InstRW<[XGeneWriteST1SfSfAlu1SfSf, XGeneWriteSTF], (instregex "STPQi$")>; +def : InstRW<[XGeneWriteST1SfSfAlu1SfSfAlu, XGeneWriteSTF], (instregex "STPQpost$")>; +def : InstRW<[XGeneWriteST1SfSfAlu1SfSfAlu, XGeneWriteSTF], (instregex "STPQpre$")>; //--- // Vector Store (66 groups in total) @@ -1488,79 +1437,76 @@ def : InstRW<[XGeneWriteSTF], (instregex "STP(D|S|Q)pre$")>; // 1X4Sf: ST4 (four registers) // 1X4SfAlu: ST4 (four registers pre/post indexed) //--- -def : InstRW<[XGeneWriteST1Sc], (instregex "ST1Onev(2s|4h|8b)$")>; -def : InstRW<[XGeneWriteST1ScAlu], (instregex "ST1Onev(2s|4h|8b)_POST$")>; - -def : InstRW<[XGeneWriteST1ScSc], (instregex "ST1Onev(4s|8h|16b)$")>; -def : InstRW<[XGeneWriteST1ScSc], (instregex "ST1Twov(2s|4h|8b)$")>; -def : InstRW<[XGeneWriteST1ScSc], (instregex "ST2Twov(2s|4h|8b)$")>; -def : InstRW<[XGeneWriteST1ScScAlu], (instregex "ST1Onev(4s|8h|16b)_POST$")>; -def : InstRW<[XGeneWriteST1ScScAlu], (instregex "ST1Twov(2s|4h|8b)_POST$")>; -def : InstRW<[XGeneWriteST1ScScAlu], (instregex "ST2Twov(2s|4h|8b)_POST$")>; - -def : InstRW<[XGeneWriteST1X3Sc], (instregex "ST1Threev(2s|4h|8b)$")>; -def : InstRW<[XGeneWriteST1X3Sc], (instregex "ST3Threev(2s|4h|8b)$")>; -def : InstRW<[XGeneWriteST1X3ScAlu], (instregex "ST1Threev(2s|4h|8b)_POST$")>; -def : InstRW<[XGeneWriteST1X3ScAlu], (instregex "ST3Threev(2s|4h|8b)_POST$")>; - -def : InstRW<[XGeneWriteST1X4Sc], (instregex "ST1Twov(4s|8h|16b)$")>; -def : InstRW<[XGeneWriteST1X4Sc], (instregex "ST1Fourv(2s|4h|8b)$")>; -def : InstRW<[XGeneWriteST1X4Sc], (instregex "ST2Twov(4s|8h|16b)$")>; -def : InstRW<[XGeneWriteST1X4Sc], (instregex "ST4Fourv(2s|4h|8b)$")>; -def : InstRW<[XGeneWriteST1X4ScAlu], (instregex "ST1Twov(4s|8h|16b)_POST$")>; -def : InstRW<[XGeneWriteST1X4ScAlu], (instregex "ST1Fourv(2s|4h|8b)_POST$")>; -def : InstRW<[XGeneWriteST1X4ScAlu], (instregex "ST2Twov(4s|8h|16b)_POST$")>; -def : InstRW<[XGeneWriteST1X4ScAlu], (instregex "ST4Fourv(2s|4h|8b)_POST$")>; - -def : InstRW<[XGeneWriteST1X6Sc], (instregex "ST1Threev(4s|8h|16b)$")>; -def : InstRW<[XGeneWriteST1X6Sc], (instregex "ST3Threev(4s|8h|16b)$")>; -def : InstRW<[XGeneWriteST1X6ScAlu], (instregex "ST1Threev(4s|8h|16b)_POST$")>; -def : InstRW<[XGeneWriteST1X6ScAlu], (instregex "ST3Threev(4s|8h|16b)_POST$")>; - -def : InstRW<[XGeneWriteST1X8Sc], (instregex "ST1Fourv(4s|8h|16b)$")>; -def : InstRW<[XGeneWriteST1X8Sc], (instregex "ST4Fourv(4s|8h|16b)$")>; -def : InstRW<[XGeneWriteST1X8ScAlu], (instregex "ST1Fourv(4s|8h|16b)_POST$")>; -def : InstRW<[XGeneWriteST1X8ScAlu], (instregex "ST4Fourv(4s|8h|16b)_POST$")>; - -def : InstRW<[XGeneWriteST1Sf], (instregex "ST1Onev1d$")>; -def : InstRW<[XGeneWriteST1SfAlu], (instregex "ST1Onev1d_POST$")>; - -def : InstRW<[XGeneWriteST1SfSf], (instregex "ST1Onev2d$")>; -def : InstRW<[XGeneWriteST1SfSf], (instregex "ST1Twov1d$")>; -def : InstRW<[XGeneWriteST1SfSfAlu], (instregex "ST1Onev2d_POST$")>; -def : InstRW<[XGeneWriteST1SfSfAlu], (instregex "ST1Twov1d_POST$")>; - -def : InstRW<[XGeneWriteST1X3Sf], (instregex "ST1Threev1d$")>; -def : InstRW<[XGeneWriteST1X3SfAlu], (instregex "ST1Threev1d_POST$")>; - -def : InstRW<[XGeneWriteST1X4Sf], (instregex "ST1Twov2d$")>; -def : InstRW<[XGeneWriteST1X4Sf], (instregex "ST1Fourv1d$")>; -def : InstRW<[XGeneWriteST1X4Sf], (instregex "ST2Twov2d$")>; -def : InstRW<[XGeneWriteST1X4SfAlu], (instregex "ST1Twov2d_POST$")>; -def : InstRW<[XGeneWriteST1X4SfAlu], (instregex "ST1Fourv1d_POST$")>; -def : InstRW<[XGeneWriteST1X4SfAlu], (instregex "ST2Twov2d_POST$")>; - -def : InstRW<[XGeneWriteST1X6Sf], (instregex "ST1Threev2d$")>; -def : InstRW<[XGeneWriteST1X6Sf], (instregex "ST3Threev2d$")>; -def : InstRW<[XGeneWriteST1X6SfAlu], (instregex "ST1Threev2d_POST$")>; -def : InstRW<[XGeneWriteST1X6SfAlu], (instregex "ST3Threev2d_POST$")>; - -def : InstRW<[XGeneWriteST1X8Sf], (instregex "ST1Fourv2d$")>; -def : InstRW<[XGeneWriteST1X8Sf], (instregex "ST4Fourv2d$")>; -def : InstRW<[XGeneWriteST1X8SfAlu], (instregex "ST1Fourv2d_POST$")>; -def : InstRW<[XGeneWriteST1X8SfAlu], (instregex "ST4Fourv2d_POST$")>; - -def : InstRW<[XGeneWriteST1Sf], (instregex "ST1(i8|i16|i32|i64)$")>; -def : InstRW<[XGeneWriteST1SfAlu], (instregex "ST1(i8|i16|i32|i64)_POST$")>; -def : InstRW<[XGeneWriteST1SfSf], (instregex "ST2(i8|i16|i32|i64)$")>; -def : InstRW<[XGeneWriteST1SfSfAlu], (instregex "ST2(i8|i16|i32|i64)_POST$")>; -def : InstRW<[XGeneWriteST1X3Sf], (instregex "ST3(i8|i16|i32|i64)$")>; -def : InstRW<[XGeneWriteST1X3SfAlu], (instregex "ST3(i8|i16|i32|i64)_POST$")>; -def : InstRW<[XGeneWriteST1X4Sf], (instregex "ST4(i8|i16|i32|i64)$")>; -def : InstRW<[XGeneWriteST1X4SfAlu], (instregex "ST4(i8|i16|i32|i64)_POST$")>; - -// All vector stores for read advance, they go in the "Store Float" group -def : InstRW<[XGeneWriteSTF], (instregex "ST.*$")>; +def : InstRW<[XGeneWriteST1Sc, XGeneWriteSTF], (instregex "ST1Onev(2s|4h|8b)$")>; +def : InstRW<[XGeneWriteST1ScAlu, XGeneWriteSTF], (instregex "ST1Onev(2s|4h|8b)_POST$")>; + +def : InstRW<[XGeneWriteST1ScSc, XGeneWriteSTF], (instregex "ST1Onev(4s|8h|16b)$")>; +def : InstRW<[XGeneWriteST1ScSc, XGeneWriteSTF], (instregex "ST1Twov(2s|4h|8b)$")>; +def : InstRW<[XGeneWriteST1ScSc, XGeneWriteSTF], (instregex "ST2Twov(2s|4h|8b)$")>; +def : InstRW<[XGeneWriteST1ScScAlu, XGeneWriteSTF], (instregex "ST1Onev(4s|8h|16b)_POST$")>; +def : InstRW<[XGeneWriteST1ScScAlu, XGeneWriteSTF], (instregex "ST1Twov(2s|4h|8b)_POST$")>; +def : InstRW<[XGeneWriteST1ScScAlu, XGeneWriteSTF], (instregex "ST2Twov(2s|4h|8b)_POST$")>; + +def : InstRW<[XGeneWriteST1X3Sc, XGeneWriteSTF], (instregex "ST1Threev(2s|4h|8b)$")>; +def : InstRW<[XGeneWriteST1X3Sc, XGeneWriteSTF], (instregex "ST3Threev(2s|4h|8b)$")>; +def : InstRW<[XGeneWriteST1X3ScAlu, XGeneWriteSTF], (instregex "ST1Threev(2s|4h|8b)_POST$")>; +def : InstRW<[XGeneWriteST1X3ScAlu, XGeneWriteSTF], (instregex "ST3Threev(2s|4h|8b)_POST$")>; + +def : InstRW<[XGeneWriteST1X4Sc, XGeneWriteSTF], (instregex "ST1Twov(4s|8h|16b)$")>; +def : InstRW<[XGeneWriteST1X4Sc, XGeneWriteSTF], (instregex "ST1Fourv(2s|4h|8b)$")>; +def : InstRW<[XGeneWriteST1X4Sc, XGeneWriteSTF], (instregex "ST2Twov(4s|8h|16b)$")>; +def : InstRW<[XGeneWriteST1X4Sc, XGeneWriteSTF], (instregex "ST4Fourv(2s|4h|8b)$")>; +def : InstRW<[XGeneWriteST1X4ScAlu, XGeneWriteSTF], (instregex "ST1Twov(4s|8h|16b)_POST$")>; +def : InstRW<[XGeneWriteST1X4ScAlu, XGeneWriteSTF], (instregex "ST1Fourv(2s|4h|8b)_POST$")>; +def : InstRW<[XGeneWriteST1X4ScAlu, XGeneWriteSTF], (instregex "ST2Twov(4s|8h|16b)_POST$")>; +def : InstRW<[XGeneWriteST1X4ScAlu, XGeneWriteSTF], (instregex "ST4Fourv(2s|4h|8b)_POST$")>; + +def : InstRW<[XGeneWriteST1X6Sc, XGeneWriteSTF], (instregex "ST1Threev(4s|8h|16b)$")>; +def : InstRW<[XGeneWriteST1X6Sc, XGeneWriteSTF], (instregex "ST3Threev(4s|8h|16b)$")>; +def : InstRW<[XGeneWriteST1X6ScAlu, XGeneWriteSTF], (instregex "ST1Threev(4s|8h|16b)_POST$")>; +def : InstRW<[XGeneWriteST1X6ScAlu, XGeneWriteSTF], (instregex "ST3Threev(4s|8h|16b)_POST$")>; + +def : InstRW<[XGeneWriteST1X8Sc, XGeneWriteSTF], (instregex "ST1Fourv(4s|8h|16b)$")>; +def : InstRW<[XGeneWriteST1X8Sc, XGeneWriteSTF], (instregex "ST4Fourv(4s|8h|16b)$")>; +def : InstRW<[XGeneWriteST1X8ScAlu, XGeneWriteSTF], (instregex "ST1Fourv(4s|8h|16b)_POST$")>; +def : InstRW<[XGeneWriteST1X8ScAlu, XGeneWriteSTF], (instregex "ST4Fourv(4s|8h|16b)_POST$")>; + +def : InstRW<[XGeneWriteST1Sf, XGeneWriteSTF], (instregex "ST1Onev1d$")>; +def : InstRW<[XGeneWriteST1SfAlu, XGeneWriteSTF], (instregex "ST1Onev1d_POST$")>; + +def : InstRW<[XGeneWriteST1SfSf, XGeneWriteSTF], (instregex "ST1Onev2d$")>; +def : InstRW<[XGeneWriteST1SfSf, XGeneWriteSTF], (instregex "ST1Twov1d$")>; +def : InstRW<[XGeneWriteST1SfSfAlu, XGeneWriteSTF], (instregex "ST1Onev2d_POST$")>; +def : InstRW<[XGeneWriteST1SfSfAlu, XGeneWriteSTF], (instregex "ST1Twov1d_POST$")>; + +def : InstRW<[XGeneWriteST1X3Sf, XGeneWriteSTF], (instregex "ST1Threev1d$")>; +def : InstRW<[XGeneWriteST1X3SfAlu, XGeneWriteSTF], (instregex "ST1Threev1d_POST$")>; + +def : InstRW<[XGeneWriteST1X4Sf, XGeneWriteSTF], (instregex "ST1Twov2d$")>; +def : InstRW<[XGeneWriteST1X4Sf, XGeneWriteSTF], (instregex "ST1Fourv1d$")>; +def : InstRW<[XGeneWriteST1X4Sf, XGeneWriteSTF], (instregex "ST2Twov2d$")>; +def : InstRW<[XGeneWriteST1X4SfAlu, XGeneWriteSTF], (instregex "ST1Twov2d_POST$")>; +def : InstRW<[XGeneWriteST1X4SfAlu, XGeneWriteSTF], (instregex "ST1Fourv1d_POST$")>; +def : InstRW<[XGeneWriteST1X4SfAlu, XGeneWriteSTF], (instregex "ST2Twov2d_POST$")>; + +def : InstRW<[XGeneWriteST1X6Sf, XGeneWriteSTF], (instregex "ST1Threev2d$")>; +def : InstRW<[XGeneWriteST1X6Sf, XGeneWriteSTF], (instregex "ST3Threev2d$")>; +def : InstRW<[XGeneWriteST1X6SfAlu, XGeneWriteSTF], (instregex "ST1Threev2d_POST$")>; +def : InstRW<[XGeneWriteST1X6SfAlu, XGeneWriteSTF], (instregex "ST3Threev2d_POST$")>; + +def : InstRW<[XGeneWriteST1X8Sf, XGeneWriteSTF], (instregex "ST1Fourv2d$")>; +def : InstRW<[XGeneWriteST1X8Sf, XGeneWriteSTF], (instregex "ST4Fourv2d$")>; +def : InstRW<[XGeneWriteST1X8SfAlu, XGeneWriteSTF], (instregex "ST1Fourv2d_POST$")>; +def : InstRW<[XGeneWriteST1X8SfAlu, XGeneWriteSTF], (instregex "ST4Fourv2d_POST$")>; + +def : InstRW<[XGeneWriteST1Sf, XGeneWriteSTF], (instregex "ST1(i8|i16|i32|i64)$")>; +def : InstRW<[XGeneWriteST1SfAlu, XGeneWriteSTF], (instregex "ST1(i8|i16|i32|i64)_POST$")>; +def : InstRW<[XGeneWriteST1SfSf, XGeneWriteSTF], (instregex "ST2(i8|i16|i32|i64)$")>; +def : InstRW<[XGeneWriteST1SfSfAlu, XGeneWriteSTF], (instregex "ST2(i8|i16|i32|i64)_POST$")>; +def : InstRW<[XGeneWriteST1X3Sf, XGeneWriteSTF], (instregex "ST3(i8|i16|i32|i64)$")>; +def : InstRW<[XGeneWriteST1X3SfAlu, XGeneWriteSTF], (instregex "ST3(i8|i16|i32|i64)_POST$")>; +def : InstRW<[XGeneWriteST1X4Sf, XGeneWriteSTF], (instregex "ST4(i8|i16|i32|i64)$")>; +def : InstRW<[XGeneWriteST1X4SfAlu, XGeneWriteSTF], (instregex "ST4(i8|i16|i32|i64)_POST$")>; //--- // Data Processing Register @@ -1590,10 +1536,10 @@ def : InstRW<[XGeneWriteI1Alb1Alu], (instregex "RORV(W|X)r$")>; def : InstRW<[XGeneWriteI1Sbfm], (instregex "SBFM(W|X)ri$")>; def : InstRW<[XGeneWriteI1Car], (instregex "ADC(W|X)r$")>; -def : InstRW<[XGeneWriteI1Car], (instregex "ADCS(W|X)r$")>; -def : InstRW<[XGeneWriteI1Set], (instregex "CCMP(W|X)r$")>; -def : InstRW<[XGeneWriteI1Set], (instregex "CCMP(W|X)i$")>; -def : InstRW<[XGeneWriteI1Alu], (instregex "CSEL(W|X)r$")>; +def : InstRW<[XGeneWriteI1Car, XGeneWriteISFlags], (instregex "ADCS(W|X)r$")>; +def : InstRW<[XGeneWriteI1Set, XGeneReadISFlags], (instregex "CCMP(W|X)r$")>; +def : InstRW<[XGeneWriteI1Set, XGeneReadISFlags], (instregex "CCMP(W|X)i$")>; +def : InstRW<[XGeneWriteI1Alu, XGeneReadISFlags], (instregex "CSEL(W|X)r$")>; def : InstRW<[XGeneWriteI1Mlw1Alu], (instregex "MADD(W)rrr$")>; def : InstRW<[XGeneWriteI1Mlx1Alu], (instregex "MADD(X)rrr$")>; @@ -1621,31 +1567,31 @@ def : InstRW<[XGeneWriteI1Alu], (instregex "MSR$")>; // Taken form list of missing instructions def : InstRW<[XGeneWriteI1Alu], (instregex "ADD(W|X)r(r|i)$")>; def : InstRW<[XGeneWriteI1Alb1Alu], (instregex "ADD(W|X)rx$")>; -def : InstRW<[XGeneWriteI1Set], (instregex "ADDS(W|X)r(r|i)$")>; -def : InstRW<[XGeneWriteI1Alb1Alu], (instregex "ADDS(W|X)rx$")>; +def : InstRW<[XGeneWriteI1Set, XGeneWriteISFlags], (instregex "ADDS(W|X)r(r|i)$")>; +def : InstRW<[XGeneWriteI1Alb1Alu, XGeneWriteISFlags], (instregex "ADDS(W|X)rx$")>; def : InstRW<[XGeneWriteI1Alu], (instregex "SUB(W|X)r(r|i)$")>; def : InstRW<[XGeneWriteI1Alb1Alu], (instregex "SUB(W|X)rx$")>; -def : InstRW<[XGeneWriteI1Set], (instregex "SUBS(W|X)r(r|i)$")>; -def : InstRW<[XGeneWriteI1Alb1Alu], (instregex "SUBS(W|X)rx$")>; +def : InstRW<[XGeneWriteI1Set, XGeneWriteISFlags], (instregex "SUBS(W|X)r(r|i)$")>; +def : InstRW<[XGeneWriteI1Alb1Alu, XGeneWriteISFlags], (instregex "SUBS(W|X)rx$")>; def : InstRW<[XGeneWriteI1Alu], (instregex "AND(W|X)r(r|i)$")>; -def : InstRW<[XGeneWriteI1Set], (instregex "ANDS(W|X)r(r|i)$")>; +def : InstRW<[XGeneWriteI1Set, XGeneWriteISFlags], (instregex "ANDS(W|X)r(r|i)$")>; def : InstRW<[XGeneWriteI1Alu], (instregex "BIC(W|X)rr$")>; -def : InstRW<[XGeneWriteI1Set], (instregex "BICS(W|X)rr$")>; +def : InstRW<[XGeneWriteI1Set, XGeneWriteISFlags], (instregex "BICS(W|X)rr$")>; def : InstRW<[XGeneWriteI1Alu], (instregex "EON(W|X)rr$")>; def : InstRW<[XGeneWriteI1Alu], (instregex "EOR(W|X)r(r|i)$")>; def : InstRW<[XGeneWriteI1Alu], (instregex "ORN(W|X)rr$")>; def : InstRW<[XGeneWriteI1Alu], (instregex "ORR(W|X)r(r|i)$")>; -def : InstRW<[XGeneWriteI1Alu], (instregex "CLS(W|X)r$")>; -def : InstRW<[XGeneWriteI1Alu], (instregex "CLZ(W|X)r$")>; +def : InstRW<[XGeneWriteI1Alu, XGeneReadISFlags], (instregex "CLS(W|X)r$")>; +def : InstRW<[XGeneWriteI1Alu, XGeneReadISFlags], (instregex "CLZ(W|X)r$")>; def : InstRW<[XGeneWriteI1Alu], (instregex "RBIT(W|X)r$")>; -def : InstRW<[XGeneWriteI1Alu], (instregex "CSINC(W|X)r$")>; -def : InstRW<[XGeneWriteI1Alu], (instregex "CSINV(W|X)r$")>; -def : InstRW<[XGeneWriteI1Alu], (instregex "CSNEG(W|X)r$")>; +def : InstRW<[XGeneWriteI1Alu, XGeneReadISFlags], (instregex "CSINC(W|X)r$")>; +def : InstRW<[XGeneWriteI1Alu, XGeneReadISFlags], (instregex "CSINV(W|X)r$")>; +def : InstRW<[XGeneWriteI1Alu, XGeneReadISFlags], (instregex "CSNEG(W|X)r$")>; def : InstRW<[XGeneWriteI1Car], (instregex "SBC(W|X)r$")>; -def : InstRW<[XGeneWriteI1Car], (instregex "SBCS(W|X)r$")>; +def : InstRW<[XGeneWriteI1Car, XGeneWriteISFlags], (instregex "SBCS(W|X)r$")>; def : InstRW<[XGeneWriteI1Alb], (instregex "EXTR(W|X)rri$")>; def : InstRW<[XGeneWriteI1Alu], (instregex "MOV(N|Z|K)(W|X)i$")>; @@ -1653,12 +1599,12 @@ def : InstRW<[XGeneWriteI1Alu], (instregex "MOV(N|Z|K)(W|X)i$")>; def : InstRW<[XGeneWriteI1Alu], (instregex "ADR$")>; def : InstRW<[XGeneWriteI1Alu], (instregex "ADRP$")>; -def : InstRW<[XGeneWriteI1Set], (instregex "CCMN(W|X)(r|i)$")>; +def : InstRW<[XGeneWriteI1Set, XGeneReadISFlags], (instregex "CCMN(W|X)(r|i)$")>; def : InstRW<[XGeneWriteI1Alu], (instregex "TBZ(W|X)$")>; def : InstRW<[XGeneWriteI1Alu], (instregex "TBNZ(W|X)$")>; -def : InstRW<[XGeneWriteI1Alu], (instregex "CBZ(W|X)$")>; -def : InstRW<[XGeneWriteI1Alu], (instregex "CBNZ(W|X)$")>; +def : InstRW<[XGeneWriteI1Alu, XGeneReadISFlags], (instregex "CBZ(W|X)$")>; +def : InstRW<[XGeneWriteI1Alu, XGeneReadISFlags], (instregex "CBNZ(W|X)$")>; // shifted def : InstRW<[XGeneWriteI1Sbfm1Alu], (instregex "ADD(W|X)rs$")>; @@ -1675,27 +1621,6 @@ def : InstRW<[XGeneWriteI1Sbfm1Alu], (instregex "EOR(W|X)rs$")>; def : InstRW<[XGeneWriteI1Sbfm1Alu], (instregex "ORN(W|X)rs$")>; def : InstRW<[XGeneWriteI1Sbfm1Alu], (instregex "ORR(W|X)rs$")>; -def : InstRW<[XGeneWriteISFlags], (instregex "ADCS(W|X)r$")>; -def : InstRW<[XGeneWriteISFlags], (instregex "ADDS(W|X)r(r|i)$")>; -def : InstRW<[XGeneWriteISFlags], (instregex "ADDS(W|X)rx$")>; -def : InstRW<[XGeneWriteISFlags], (instregex "SUBS(W|X)r(r|i)$")>; -def : InstRW<[XGeneWriteISFlags], (instregex "SUBS(W|X)rx$")>; -def : InstRW<[XGeneWriteISFlags], (instregex "ANDS(W|X)r(r|i)$")>; -def : InstRW<[XGeneWriteISFlags], (instregex "BICS(W|X)rr$")>; -def : InstRW<[XGeneWriteISFlags], (instregex "SBCS(W|X)r$")>; - -def : InstRW<[XGeneReadISFlags], (instregex "CCMP(W|X)r$")>; -def : InstRW<[XGeneReadISFlags], (instregex "CCMP(W|X)i$")>; -def : InstRW<[XGeneReadISFlags], (instregex "CSEL(W|X)r$")>; -def : InstRW<[XGeneReadISFlags], (instregex "CLS(W|X)r$")>; -def : InstRW<[XGeneReadISFlags], (instregex "CLZ(W|X)r$")>; -def : InstRW<[XGeneReadISFlags], (instregex "CSINC(W|X)r$")>; -def : InstRW<[XGeneReadISFlags], (instregex "CSINV(W|X)r$")>; -def : InstRW<[XGeneReadISFlags], (instregex "CSNEG(W|X)r$")>; -def : InstRW<[XGeneReadISFlags], (instregex "CCMN(W|X)(r|i)$")>; -def : InstRW<[XGeneReadISFlags], (instregex "CBZ(W|X)$")>; -def : InstRW<[XGeneReadISFlags], (instregex "CBNZ(W|X)$")>; - // TODO: STLX et al. //--- @@ -2209,9 +2134,6 @@ def : InstRW<[XGeneWriteVI1AssAss], (instregex "ZIP(1|2)v(16i8|4i32|2i64)$")>; def : InstRW<[XGeneWriteVI1AssAss], (instregex "UZP(1|2)v(16i8|4i32|2i64)$")>; def : InstRW<[XGeneWriteVI1AssAss], (instregex "TRN(1|2)v(16i8|4i32|2i64)$")>; -//def : InstRW<[XGeneWriteVI1AslAsl], (instregex "^ZIP(1|2)_(PPP|ZZZ)_(B|D|H|S)$")>; - - //--- // AdvSIMD Data Processing (Vector Integer) // AdvSIMD EXT: -- cgit v1.2.3