From 22a047b7bdc982e02c510d72d640d66cd34b8c4d Mon Sep 17 00:00:00 2001 From: Hans Wennborg Date: Tue, 20 Feb 2018 16:18:57 +0000 Subject: Merging r325550: I couldn't get fp16-copy-gpr.mir to pass after merging so I removed it until aemerson; the other test I re-generated and it seems to work. ------------------------------------------------------------------------ r325550 | aemerson | 2018-02-20 06:11:57 +0100 (Tue, 20 Feb 2018) | 7 lines [AArch64][GlobalISel] When copying from a gpr32 to an fpr16 reg, convert to fpr32 first. This is a follow on commit to r[x] where we fix the other direction of copy. For this case, after converting the source from gpr32 -> fpr32, we use a subregister copy, which is essentially what EXTRACT_SUBREG does in SDAG land. https://reviews.llvm.org/D43444 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@325591 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64InstructionSelector.cpp | 35 ++++++++- test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir | 90 ----------------------- 2 files changed, 31 insertions(+), 94 deletions(-) delete mode 100644 test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir diff --git a/lib/Target/AArch64/AArch64InstructionSelector.cpp b/lib/Target/AArch64/AArch64InstructionSelector.cpp index a5fe398e7ea..61687c927b2 100644 --- a/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -315,12 +315,39 @@ static unsigned selectLoadStoreUIOp(unsigned GenericOpc, unsigned RegBankID, return GenericOpc; } +static bool selectFP16CopyFromGPR32(MachineInstr &I, const TargetInstrInfo &TII, + MachineRegisterInfo &MRI, unsigned SrcReg) { + // Copies from gpr32 to fpr16 need to use a sub-register copy. + unsigned CopyReg = MRI.createVirtualRegister(&AArch64::FPR32RegClass); + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AArch64::COPY)) + .addDef(CopyReg) + .addUse(SrcReg); + unsigned SubRegCopy = MRI.createVirtualRegister(&AArch64::FPR16RegClass); + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::COPY)) + .addDef(SubRegCopy) + .addUse(CopyReg, 0, AArch64::hsub); + + MachineOperand &RegOp = I.getOperand(1); + RegOp.setReg(SubRegCopy); + return true; +} + static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) { unsigned DstReg = I.getOperand(0).getReg(); + unsigned SrcReg = I.getOperand(1).getReg(); + if (TargetRegisterInfo::isPhysicalRegister(DstReg)) { + if (TRI.getRegClass(AArch64::FPR16RegClassID)->contains(DstReg) && + !TargetRegisterInfo::isPhysicalRegister(SrcReg)) { + const RegisterBank &RegBank = *RBI.getRegBank(SrcReg, MRI, TRI); + const TargetRegisterClass *SrcRC = getRegClassForTypeOnBank( + MRI.getType(SrcReg), RegBank, RBI, /* GetAllRegSet */ true); + if (SrcRC == &AArch64::GPR32allRegClass) + return selectFP16CopyFromGPR32(I, TII, MRI, SrcReg); + } assert(I.isCopy() && "Generic operators do not allow physical registers"); return true; } @@ -328,7 +355,6 @@ static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); const unsigned DstSize = MRI.getType(DstReg).getSizeInBits(); (void)DstSize; - unsigned SrcReg = I.getOperand(1).getReg(); const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI); (void)SrcSize; assert((!TargetRegisterInfo::isPhysicalRegister(SrcReg) || I.isCopy()) && @@ -355,9 +381,7 @@ static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, } if (!TargetRegisterInfo::isPhysicalRegister(SrcReg)) { - const RegClassOrRegBank &RegClassOrBank = - MRI.getRegClassOrRegBank(SrcReg); - + const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(SrcReg); const TargetRegisterClass *SrcRC = RegClassOrBank.dyn_cast(); const RegisterBank *RB = nullptr; @@ -376,6 +400,9 @@ static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, .addImm(AArch64::hsub); MachineOperand &RegOp = I.getOperand(1); RegOp.setReg(PromoteReg); + } else if (RC == &AArch64::FPR16RegClass && + SrcRC == &AArch64::GPR32allRegClass) { + selectFP16CopyFromGPR32(I, TII, MRI, SrcReg); } } diff --git a/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir b/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir deleted file mode 100644 index fb5af0a8f10..00000000000 --- a/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir +++ /dev/null @@ -1,90 +0,0 @@ -# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=aarch64-unknown-unknown -o - -global-isel -verify-machineinstrs -run-pass=instruction-select %s | FileCheck %s - -# PR36345 ---- | - target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" - target triple = "aarch64-arm-none-eabi" - - %struct.struct2 = type { [2 x half] } - - @global_arg0 = common dso_local global %struct.struct2 zeroinitializer, align 2 - - ; Function Attrs: noinline nounwind optnone - define dso_local void @c_test([2 x half], [2 x half]* %addr) { - ; CHECK-LABEL: name: c_test - ; CHECK: bb.0 (%ir-block.1): - ; CHECK: liveins: %h0, %h1, %x0 - ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY %h0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr16 = COPY %h1 - ; CHECK: [[DEF:%[0-9]+]]:gpr64 = IMPLICIT_DEF - ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub - ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG]] - ; CHECK: [[SUBREG_TO_REG1:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY2]], %subreg.sub_32 - ; CHECK: [[BFMXri:%[0-9]+]]:gpr64 = BFMXri [[DEF]], [[SUBREG_TO_REG1]], 0, 15 - ; CHECK: [[SUBREG_TO_REG2:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub - ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG2]] - ; CHECK: [[SUBREG_TO_REG3:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY3]], %subreg.sub_32 - ; CHECK: [[BFMXri1:%[0-9]+]]:gpr64 = BFMXri [[BFMXri]], [[SUBREG_TO_REG3]], 48, 15 - ; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY [[BFMXri1]] - ; CHECK: [[COPY5:%[0-9]+]]:gpr64sp = COPY %x0 - ; CHECK: STRWui [[COPY4]], [[COPY5]], 0 :: (store 4 into %ir.addr, align 2) - ; CHECK: RET_ReallyLR - store [2 x half] %0, [2 x half]* %addr, align 2 - ret void - } -... ---- -name: c_test -alignment: 2 -legalized: true -regBankSelected: true -tracksRegLiveness: true -registers: - - { id: 0, class: gpr } - - { id: 1, class: fpr } - - { id: 2, class: fpr } - - { id: 3, class: gpr } - - { id: 4, class: gpr } - - { id: 5, class: gpr } - - { id: 6, class: gpr } - - { id: 7, class: gpr } - - { id: 8, class: gpr } - - { id: 9, class: gpr } - - { id: 10, class: gpr } - - { id: 11, class: gpr } - - { id: 12, class: gpr } -body: | - bb.1 (%ir-block.1): - liveins: %h0, %h1, %x0 - - ; CHECK-LABEL: name: c_test - ; CHECK: liveins: %h0, %h1, %x0 - ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY %h0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr16 = COPY %h1 - ; CHECK: [[DEF:%[0-9]+]]:gpr64 = IMPLICIT_DEF - ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub - ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG]] - ; CHECK: [[SUBREG_TO_REG1:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY2]], %subreg.sub_32 - ; CHECK: [[BFMXri:%[0-9]+]]:gpr64 = BFMXri [[DEF]], [[SUBREG_TO_REG1]], 0, 15 - ; CHECK: [[SUBREG_TO_REG2:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub - ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG2]] - ; CHECK: [[SUBREG_TO_REG3:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY3]], %subreg.sub_32 - ; CHECK: [[BFMXri1:%[0-9]+]]:gpr64 = BFMXri [[BFMXri]], [[SUBREG_TO_REG3]], 48, 15 - ; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY [[BFMXri1]] - ; CHECK: [[COPY5:%[0-9]+]]:gpr64sp = COPY %x0 - ; CHECK: STRWui [[COPY4]], [[COPY5]], 0 :: (store 4 into %ir.addr, align 2) - ; CHECK: RET_ReallyLR - %1:fpr(s16) = COPY %h0 - %2:fpr(s16) = COPY %h1 - %3:gpr(s32) = G_IMPLICIT_DEF - %11:gpr(s16) = COPY %1(s16) - %4:gpr(s32) = G_INSERT %3, %11(s16), 0 - %12:gpr(s16) = COPY %2(s16) - %5:gpr(s32) = G_INSERT %4, %12(s16), 16 - %0:gpr(s32) = COPY %5(s32) - %6:gpr(p0) = COPY %x0 - G_STORE %0(s32), %6(p0) :: (store 4 into %ir.addr, align 2) - RET_ReallyLR - -... -- cgit v1.2.3