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2017-11-10[debuginfo-tests] Make debuginfo-tests work in a standard configuration.Zachary Turner
Previously, debuginfo-tests was expected to be checked out into clang/test and then the tests would automatically run as part of check-clang. This is not a standard workflow for handling external projects, and it brings with it some serious drawbacks such as the inability to depend on things other than clang, which we will need going forward. The goal of this patch is to migrate towards a more standard workflow. To ease the transition for build bot maintainers, this patch tries not to break the existing workflow, but instead simply deprecate it to give maintainers a chance to update the build infrastructure. Differential Revision: https://reviews.llvm.org/D39605 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317925 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10Allow separation of declarations and definitions in <Target>ISelDAGToDAG.incKrzysztof Parzyszek
This patch adds the ability to include the member function declarations in the instruction selector class separately from the member bodies. Defining GET_DAGISEL_DECL macro to any value will only include the member declarations. To include bodies, define GET_DAGISEL_BODY macro to be the selector class name. Example: class FooDAGToDAGISel : public SelectionDAGISel { // Pull in declarations only. #define GET_DAGISEL_DECL #include "FooISelDAGToDAG.inc" }; // Include the function bodies (with names qualified with the provided // class name). #define GET_DAGISEL_BODY FooDAGToDAGISel #include "FooISelDAGToDAG.inc" When neither of the two macros are defined, the function bodies are emitted inline (in the same way as before this patch). Differential Revision: https://reviews.llvm.org/D39596 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317903 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09[utils] Fix RISC-V support in update_llc_test_checks.pyAlex Bradbury
scrub_asm_riscv now takes two arguments rather than one. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317826 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-08[utils] Add RISC-V support to update_llc_test_checks.pyAlex Bradbury
This should be a trivial change, and I've started using it for generating all tests at https://github.com/lowrisc/riscv-llvm (i.e. it's been tested in action quite a lot). Note that the regex does not attempt to match .cfi_startproc, as I want to ensure compatibility with functions that have the nounwind attribute. Differential Revision: https://reviews.llvm.org/D39789 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317693 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-07Add a -D flag to FileCheck to define variablesAlexander Richardson
Summary: This makes it very easy to test files that only differ in a constant value somewhere in the test case. Reviewers: jlebar, hfinkel, chandlerc, probinson Reviewed By: probinson Subscribers: probinson, llvm-commits Differential Revision: https://reviews.llvm.org/D39629 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317572 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-07[AArch64][SVE] Asm: Extend EnforceVectorSubVectorTypeIs to distinguish ↵Florian Hahn
Scalable Vectors Patch [1/5] in a series to add assembler/disassembler support for AArch64 SVE unpredicated ADD/SUB instructions. Patch by Sander De Smalen. Reviewed by: rengolin Differential Revision: https://reviews.llvm.org/D39087 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317564 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-06update_mir_test_checks: Be careful about replacing entire vregsJustin Bogner
Previously, this could end up replacing a vreg like %14 with [[VREG1]]4, where VREG1 was the match for %1. That's obviously not correct, though it hasn't actually come up in any tests I've converted so far. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317509 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-04Move the llvm-tblgen project into the Tablegenning folder on IDEs like ↵Aaron Ballman
Visual Studio rather than leave it in the root directory. NFC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317420 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-04[X86] Teach EVEX->VEX pass to turn SHUFI32X4/SHUFF32X4/SHUFI64X/SHUFF64X2 ↵Craig Topper
into VPERM2F128/VPERM2I128. This recovers some of the tests that were changed by r317403. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317410 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-03[globalisel][tablegen] Skip src child predicatesDiana Picus
The GlobalISel TableGen backend didn't check for predicates on the source children. This caused it to generate code for ARM patterns such as SMLABB or similar, but without properly checking for the sext_16_node part of the operands. This in turn meant that we would select SMLABB instead of MLA for simple sequences such as s32 + s32 * s32, which is wrong (we want a MLA on the full operands, not just their bottom 16 bits). This patch forces TableGen to skip patterns with predicates on the src children, so it doesn't generate code for SMLABB and other similar ARM instructions at all anymore. AArch64 and X86 are not affected. Differential Revision: https://reviews.llvm.org/D39554 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317313 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-03[TableGen] Add an extra blank line to DAGISel output file to separate functions.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317298 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-01[globalisel][regbank] Warn about MIR ambiguities when register bank/class ↵Daniel Sanders
names clash. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317132 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-01[X86] Add custom code to EVEX to VEX pass to turn unmasked 128-bit ↵Craig Topper
VPALIGND/Q into VPALIGNR if the extended registers aren't being used. This will enable us to prefer VALIGND/Q during shuffle lowering in order to get the extended register encoding space when BWI isn't available. But if we end up not using the extended registers we can switch VPALIGNR for the shorter VEX encoding. Differential Revision: https://reviews.llvm.org/D39401 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317122 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-01[globalisel][tablegen] Add support for multi-insn emissionDaniel Sanders
The importer will now accept nested instructions in the result pattern such as (ADDWrr $a, (SUBWrr $b, $c)). This is only valid when the nested instruction def's a single vreg and the parent instruction consumes a single vreg where a nested instruction is specified. The importer will automatically create a vreg to connect the two using the type information from the pattern. This vreg will be constrained to the register classes given in the instruction definitions*. * REG_SEQUENCE is explicitly rejected because of this. The definition doesn't constrain to a register class and it therefore needs special handling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317117 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-01Fix warnings discovered by rL317076. [-Wunused-private-field]NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317091 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-01[globalisel][tablegen] Stop hard-coding the emitted instruction ID to 0. NFCDaniel Sanders
The next commit will add support for multi-instruction emission so we need to start allocating instruction ID's instead of hard-coding them to 0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317057 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-01Add system-linux to allow tests run with llvm-lit to restrict themselves to ↵Jake Ehrlich
linux I need a test that only runs in a reasonable amount of time on systems that have sparse files. The broadest class of systems that support sparse files are linux systems. So restricting my test to linux systems should suffice. This change adds the system-linux feature to llvm-lit so that it can be required. Differential Revision: https://reviews.llvm.org/D39482 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317055 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-31Re-commit: [globalisel][tablegen] Keep track of the insertion point while ↵Daniel Sanders
adding BuildMIAction's. NFC Multi-instruction emission needs to ensure the the instructions are generated a depth-first fashion. For example: (ADDWrr (SUBWrr a, b), c) needs to emit the SUBWrr before the ADDWrr. However, our walk over TreePatternNode's is highly context sensitive which makes it difficult to append BuildMIActions in the order we want. To fix this, we now keep track of the insertion point as we add actions. This will allow multi-insn emission to insert BuildMI's in the correct place. The previous commit failed on the Ubuntu bots using GCC 4.8. These bots lack the const_iterator forms of insert() and emplace() that were added in C++11. As a result I've switched the const_iterators to iterators. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317049 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-31Revert r317040: [globalisel][tablegen] Keep track of the insertion point ↵Daniel Sanders
while adding BuildMIAction's. NFC The same bots fail but I believe I know what the issue is now. These bots are missing the const_iterator versions of insert/emplace/etc. that were introduced in C++11. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317042 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-31Re-commit: [globalisel][tablegen] Keep track of the insertion point while ↵Daniel Sanders
adding BuildMIAction's. NFC Multi-instruction emission needs to ensure the the instructions are generated a depth-first fashion. For example: (ADDWrr (SUBWrr a, b), c) needs to emit the SUBWrr before the ADDWrr. However, our walk over TreePatternNode's is highly context sensitive which makes it difficult to append BuildMIActions in the order we want. To fix this, we now keep track of the insertion point as we add actions. This will allow multi-insn emission to insert BuildMI's in the correct place. The previous commit failed on the Ubuntu bots using GCC 4.8. These bots didn't like a call to emplace(). I've replaced it with insert() to see if it's a quirk of the C++11 support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317040 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-31Revert r317029: [globalisel][tablegen] Keep track of the insertion point ↵Daniel Sanders
while adding BuildMIAction's. NFC The Linux bots don't seem to like this usage of emplace(). Reverting while I look into it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317033 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-31[globalisel][tablegen] Keep track of the insertion point while adding ↵Daniel Sanders
BuildMIAction's. NFC Multi-instruction emission needs to ensure the the instructions are generated a depth-first fashion. For example: (ADDWrr (SUBWrr a, b), c) needs to emit the SUBWrr before the ADDWrr. However, our walk over TreePatternNode's is highly context sensitive which makes it difficult to append BuildMIActions in the order we want. To fix this, we now keep track of the insertion point as we add actions. This will allow multi-insn emission to insert BuildMI's in the correct place. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317029 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-31[globalisel][tablegen] Factor out implicit def/use renderers from ↵Daniel Sanders
createAndImportInstructionRenderer(). NFC Multi-instruction emission will require that we have separate handling for the defs between the implicitly created temporaries and the rule outputs. The former require new temporary vregs while the latter should copy existing operands. Factor out the implicit def/use renderers to minimize the code duplication when we implement that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317025 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-31[globalisel][tablegen] Add infrastructure to potentially allow BuildMIAction ↵Daniel Sanders
to choose a mutatable instruction. NFC Prepare for multiple instruction emission by allowing BuildMIAction to search for a suitable matcher that will support mutation. This patch deliberately neglects to add matchers aside from the root to preserve NFC. That said, it should be noted that until we support mutations other than just the opcode the chances of finding a non-root instruction for which canMutate() is true, is essentially zero. Furthermore in the presence of multi-instruction emission the chances of finding any instruction for which canMutate() is true is also zero. Nevertheless, we can't continue to require that all BuildMIAction's consider the root of the match to be recyclable due to the risk of recycling it twice in the same rule. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317022 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-31[globalisel][tablegen] Allow any comment in DebugCommentAction. NFCDaniel Sanders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317017 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-31Adding a shufflevector and select LLVM IR instructions fuzz toolAyman Musa
Based on similar python tool - utils/shuffle-fuzz.py - this tool extends the ability of it's previous by optionally attaching select instruction to the generated shufflevector instructions. This was mainly developed to perform exhaustive testing of the X86 AVX512 masked shuffle instructions. But yet it can be used for various other targets. The general design of the implementation is much modular than the original shuffle_fuzz.py tool, which makes it easier for anyone to extend it further. Differential Revision: https://reviews.llvm.org/D38031 Change-Id: I0efc2aaa091b61a8a9552311c21cc77916a97111 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316989 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-27Force #define GTEST_LANG_CXX11.Zachary Turner
gtest depends on this #define to determine whether it can use various classes like std::tuple, or whether it has to fall back to experimental classes in the std::tr1 namespace. The check in the current version of gtest relies on the value of the `__cplusplus` macro, but MSVC provides a non-conformant value of this macro, making it effectively impossible to detect C++11. In short, LLVM compiled with MSVC has been silently using the tr1 versions of several classes since the beginning of time. This would normally be pretty benign, except that in the latest preview of MSVC they have marked all of the tr1 classes deprecated, so it spews thousands of warnings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316798 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-26[TableGen] Use Twine instead of std::string concatenation in two calls to ↵Craig Topper
PrintFatalError. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316697 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-26[AsmParser][TableGen] Add VariantID argument to the generated mnemonic spell ↵Craig Topper
check function so it can use the correct table based on variant. I'm considering implementing the mnemonic spell checker for x86, and that would require the separate intel and att variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316641 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-26[AsmParser][TableGen] Make the generated mnemonic spell checker function a ↵Craig Topper
file local static function. Also only emit in targets that specificially request it. This is required so we don't get an unused static function error. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316640 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-24[globalisel][tablegen] Fix future undefined behaviour in r316463.Daniel Sanders
I missed a dereference of `Matched` that preceeded the new check. Thanks to Justin Bogner for spotting it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316480 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-24[globalisel][tablegen] Multi-insn emission requires that BuildMIAction ↵Daniel Sanders
support not being linked to an InstructionMatcher. NFC When multi-instruction emission is supported, it will no longer be guaranteed that every BuildMIAction has a corresponding matched instruction. BuildMIAction should support not having one to cover the case where a rule produces more instructions than it matched. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316463 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-24[TableGen] Fix some formatting quirks in the subtarget output file.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316450 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-24[TableGen] Simplify some of the subtarget emission by removing code that ↵Craig Topper
avoids printing commas at the end of arrays and enums. The C++ standard allows for trailing commas. We already do this in many other emitters. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316449 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-24[utils] make retq/retl regex an option that is off by defaultSanjay Patel
Ideally, we should compare 32- and 64-bit versions to see if the ret line is the only difference and then insert the regex only in that case. But this is a quick hack to avoid a bunch of noise as existing tests are updated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316443 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-24[globalisel][tablegen] Remove unused InstructionMatcher's. NFCDaniel Sanders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316407 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-23[globalisel][tablegen] Import stores and allow GISel to automatically ↵Daniel Sanders
substitute zero regs like WZR/XZR/$zero. This patch enables the import of stores. Unfortunately, doing so by itself, loses an optimization where storing 0 to memory makes use of WZR/XZR. To mitigate this, this patch also introduces a new feature that allows register operands to nominate a zero register. When this is done, GlobalISel will substitute (G_CONSTANT 0) with the nominated register automatically. This is currently configured to only apply to the stores. Applying it to GPR32/GPR64 register classes in general will be done after review see (https://reviews.llvm.org/D39150). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316360 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-23[X86] Fix disassembler table generation to prevent instructions tagged with ↵Craig Topper
'PS' being inherited into PD/XS/XD attribute entries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316345 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-23[X86] Update a doxygen comment in the disassembler tablegen code. NFCCraig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316309 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-23[X86] Fix disassembly of EVEX rounding control and SAE instructions.Craig Topper
Fixes PR31955. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316308 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-22[utils] Support -mtriple=powerpc64Fangrui Song
Summary: test/CodeGen/PowerPC/pr33093.ll uses both powerpc64 (big-endian) and powerpc64le while the former was unsupported. Subscribers: nemanjai Differential Revision: https://reviews.llvm.org/D39164 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316297 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-22[X86] More correctly support LIG and WIG for EVEX instructions in the ↵Craig Topper
disassembler tables. This is similar to how we generate the VEX tables. More fixes are still needed for the instructions that use EVEX.b (broadcast and embedded rounding). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316294 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-22[X86] Teach the disassembler that some instructions use VEX.W==0 without a ↵Craig Topper
corresponding VEX.W==1 instruction and we shouldn't treat them as if VEX.W is ignored. Fixes PR11304. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316285 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-21[X86] Fix disassembling of EVEX instructions to stop accidentally decoding ↵Craig Topper
the SIB index register as an XMM/YMM/ZMM register. This introduces a new operand type to encode the whether the index register should be XMM/YMM/ZMM. And new code to fixup the results created by readSIB. This has the nice effect of removing a bunch of code that hard coded the name of every GATHER and SCATTER instruction to map the index type. This fixes PR32807. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316273 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-20[utils, x86] add regex for retl/retq to reduce duplicated FileChecking (PR35003)Sanjay Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316242 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-20[globalisel][tablegen] Fix small spelling nits. NFCDaniel Sanders
ComplexRendererFn -> ComplexRendererFns Corrected a couple lingering references to tied operands that were missed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316237 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-18update_mir_test_checks: Support adding checks for vreg classesJustin Bogner
This is a temporary hack to support adding checks for the "registers:" block of mir functions. This is necessary to convert a number of tests so that there's less churn when we change the MIR printer to put the vreg classes on defs instead of in their own block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316134 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-18update_mir_test_checks: Improve message when updating failsJustin Bogner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316133 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-18update_mir_test_checks: Handle empty liveinsJustin Bogner
An empty livein block doesn't make much sense (why not just omit it?) but they're legal and some tests have them, so its best to handle it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316089 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-18update_mir_test_checks: Do a better job of disambiguating namesJustin Bogner
Matching prefixes isn't good enough, because it leads to things like calling the first constant C3 just because there were two copies before it. Tighten up the check to match more precisely, but also be careful about ambiguity when dealing with target opcodes that end in a number. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316088 91177308-0d34-0410-b5e6-96231b3b80d8
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