summaryrefslogtreecommitdiff
path: root/utils
AgeCommit message (Collapse)Author
2017-10-31[globalisel][tablegen] Factor out implicit def/use renderers from ↵Daniel Sanders
createAndImportInstructionRenderer(). NFC Multi-instruction emission will require that we have separate handling for the defs between the implicitly created temporaries and the rule outputs. The former require new temporary vregs while the latter should copy existing operands. Factor out the implicit def/use renderers to minimize the code duplication when we implement that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317025 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-31[globalisel][tablegen] Add infrastructure to potentially allow BuildMIAction ↵Daniel Sanders
to choose a mutatable instruction. NFC Prepare for multiple instruction emission by allowing BuildMIAction to search for a suitable matcher that will support mutation. This patch deliberately neglects to add matchers aside from the root to preserve NFC. That said, it should be noted that until we support mutations other than just the opcode the chances of finding a non-root instruction for which canMutate() is true, is essentially zero. Furthermore in the presence of multi-instruction emission the chances of finding any instruction for which canMutate() is true is also zero. Nevertheless, we can't continue to require that all BuildMIAction's consider the root of the match to be recyclable due to the risk of recycling it twice in the same rule. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317022 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-31[globalisel][tablegen] Allow any comment in DebugCommentAction. NFCDaniel Sanders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317017 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-31Adding a shufflevector and select LLVM IR instructions fuzz toolAyman Musa
Based on similar python tool - utils/shuffle-fuzz.py - this tool extends the ability of it's previous by optionally attaching select instruction to the generated shufflevector instructions. This was mainly developed to perform exhaustive testing of the X86 AVX512 masked shuffle instructions. But yet it can be used for various other targets. The general design of the implementation is much modular than the original shuffle_fuzz.py tool, which makes it easier for anyone to extend it further. Differential Revision: https://reviews.llvm.org/D38031 Change-Id: I0efc2aaa091b61a8a9552311c21cc77916a97111 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316989 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-27Force #define GTEST_LANG_CXX11.Zachary Turner
gtest depends on this #define to determine whether it can use various classes like std::tuple, or whether it has to fall back to experimental classes in the std::tr1 namespace. The check in the current version of gtest relies on the value of the `__cplusplus` macro, but MSVC provides a non-conformant value of this macro, making it effectively impossible to detect C++11. In short, LLVM compiled with MSVC has been silently using the tr1 versions of several classes since the beginning of time. This would normally be pretty benign, except that in the latest preview of MSVC they have marked all of the tr1 classes deprecated, so it spews thousands of warnings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316798 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-26[TableGen] Use Twine instead of std::string concatenation in two calls to ↵Craig Topper
PrintFatalError. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316697 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-26[AsmParser][TableGen] Add VariantID argument to the generated mnemonic spell ↵Craig Topper
check function so it can use the correct table based on variant. I'm considering implementing the mnemonic spell checker for x86, and that would require the separate intel and att variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316641 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-26[AsmParser][TableGen] Make the generated mnemonic spell checker function a ↵Craig Topper
file local static function. Also only emit in targets that specificially request it. This is required so we don't get an unused static function error. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316640 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-24[globalisel][tablegen] Fix future undefined behaviour in r316463.Daniel Sanders
I missed a dereference of `Matched` that preceeded the new check. Thanks to Justin Bogner for spotting it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316480 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-24[globalisel][tablegen] Multi-insn emission requires that BuildMIAction ↵Daniel Sanders
support not being linked to an InstructionMatcher. NFC When multi-instruction emission is supported, it will no longer be guaranteed that every BuildMIAction has a corresponding matched instruction. BuildMIAction should support not having one to cover the case where a rule produces more instructions than it matched. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316463 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-24[TableGen] Fix some formatting quirks in the subtarget output file.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316450 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-24[TableGen] Simplify some of the subtarget emission by removing code that ↵Craig Topper
avoids printing commas at the end of arrays and enums. The C++ standard allows for trailing commas. We already do this in many other emitters. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316449 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-24[utils] make retq/retl regex an option that is off by defaultSanjay Patel
Ideally, we should compare 32- and 64-bit versions to see if the ret line is the only difference and then insert the regex only in that case. But this is a quick hack to avoid a bunch of noise as existing tests are updated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316443 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-24[globalisel][tablegen] Remove unused InstructionMatcher's. NFCDaniel Sanders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316407 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-23[globalisel][tablegen] Import stores and allow GISel to automatically ↵Daniel Sanders
substitute zero regs like WZR/XZR/$zero. This patch enables the import of stores. Unfortunately, doing so by itself, loses an optimization where storing 0 to memory makes use of WZR/XZR. To mitigate this, this patch also introduces a new feature that allows register operands to nominate a zero register. When this is done, GlobalISel will substitute (G_CONSTANT 0) with the nominated register automatically. This is currently configured to only apply to the stores. Applying it to GPR32/GPR64 register classes in general will be done after review see (https://reviews.llvm.org/D39150). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316360 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-23[X86] Fix disassembler table generation to prevent instructions tagged with ↵Craig Topper
'PS' being inherited into PD/XS/XD attribute entries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316345 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-23[X86] Update a doxygen comment in the disassembler tablegen code. NFCCraig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316309 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-23[X86] Fix disassembly of EVEX rounding control and SAE instructions.Craig Topper
Fixes PR31955. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316308 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-22[utils] Support -mtriple=powerpc64Fangrui Song
Summary: test/CodeGen/PowerPC/pr33093.ll uses both powerpc64 (big-endian) and powerpc64le while the former was unsupported. Subscribers: nemanjai Differential Revision: https://reviews.llvm.org/D39164 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316297 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-22[X86] More correctly support LIG and WIG for EVEX instructions in the ↵Craig Topper
disassembler tables. This is similar to how we generate the VEX tables. More fixes are still needed for the instructions that use EVEX.b (broadcast and embedded rounding). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316294 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-22[X86] Teach the disassembler that some instructions use VEX.W==0 without a ↵Craig Topper
corresponding VEX.W==1 instruction and we shouldn't treat them as if VEX.W is ignored. Fixes PR11304. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316285 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-21[X86] Fix disassembling of EVEX instructions to stop accidentally decoding ↵Craig Topper
the SIB index register as an XMM/YMM/ZMM register. This introduces a new operand type to encode the whether the index register should be XMM/YMM/ZMM. And new code to fixup the results created by readSIB. This has the nice effect of removing a bunch of code that hard coded the name of every GATHER and SCATTER instruction to map the index type. This fixes PR32807. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316273 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-20[utils, x86] add regex for retl/retq to reduce duplicated FileChecking (PR35003)Sanjay Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316242 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-20[globalisel][tablegen] Fix small spelling nits. NFCDaniel Sanders
ComplexRendererFn -> ComplexRendererFns Corrected a couple lingering references to tied operands that were missed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316237 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-18update_mir_test_checks: Support adding checks for vreg classesJustin Bogner
This is a temporary hack to support adding checks for the "registers:" block of mir functions. This is necessary to convert a number of tests so that there's less churn when we change the MIR printer to put the vreg classes on defs instead of in their own block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316134 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-18update_mir_test_checks: Improve message when updating failsJustin Bogner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316133 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-18update_mir_test_checks: Handle empty liveinsJustin Bogner
An empty livein block doesn't make much sense (why not just omit it?) but they're legal and some tests have them, so its best to handle it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316089 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-18update_mir_test_checks: Do a better job of disambiguating namesJustin Bogner
Matching prefixes isn't good enough, because it leads to things like calling the first constant C3 just because there were two copies before it. Tighten up the check to match more precisely, but also be careful about ambiguity when dealing with target opcodes that end in a number. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316088 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-18update_mir_test_checks: Support '-' in function namesJustin Bogner
Some AArch64 and AMDGPU tests have functions with hyphens in the names git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316063 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-18update_mir_test_checks: Fix a typo I made while preparing for commitJustin Bogner
I accidentally added an extra arg here, so this didn't work at all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316062 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-18Add a utility to update MIR checks, similar to update_llc_test_checksJustin Bogner
This adds update_mir_test_checks, which updates the check lines in mir tests. This can only update tests that start and end with .mir currently (ie, -run-pass) but it should be sufficient for updating at least some of the GlobalISel tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316057 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-17lit: Improve %: normalization.Peter Collingbourne
The new scheme should match the normalization of embedded paths in linkrepro tar files. Differential Revision: https://reviews.llvm.org/D39023 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316044 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-16Revert MSVC 2017 build fix and fix it by moving the method that implicitly ↵Reid Kleckner
instantiates addPredicate out of line git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315932 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-16Fix the build of GlobalISelEmitter with MSVC 2017 by specializing earlierReid Kleckner
MSVC doesn't seem to like implicitly instantiating addPredicate and then explicitly specializing it later. It causes an internal compiler error. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315930 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-16[TableGen] Simplify CallingConvEmitter.cpp. NFC.Javed Absar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315911 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-16[TableGen] Range loopify DAGISelMatcher. NFC.Javed Absar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315891 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-16Re-commit r315885: [globalisel][tblgen] Add support for iPTR and implement ↵Daniel Sanders
am_unscaled* and am_indexed* Summary: iPTR is a pointer of subtarget-specific size to any address space. Therefore type checks on this size derive the SizeInBits from a subtarget hook. At this point, we can import the simplests G_LOAD rules and select load instructions using them. Further patches will support for the predicates to enable additional loads as well as the stores. The previous commit failed on MSVC due to a failure to convert an initializer_list to a std::vector. Hopefully, MSVC will accept this version. Depends on D37457 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37458 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315887 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-16Revert r315885: [globalisel][tblgen] Add support for iPTR and implement ↵Daniel Sanders
am_unscaled* and am_indexed* MSVC doesn't like one of the constructors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315886 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-16[globalisel][tblgen] Add support for iPTR and implement am_unscaled* and ↵Daniel Sanders
am_indexed* Summary: iPTR is a pointer of subtarget-specific size to any address space. Therefore type checks on this size derive the SizeInBits from a subtarget hook. At this point, we can import the simplests G_LOAD rules and select load instructions using them. Further patches will support for the predicates to enable additional loads as well as the stores. Depends on D37457 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37458 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315885 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-16[globalisel][tablegen] Implement unindexed load, non-extending load, and ↵Daniel Sanders
MemVT checks Summary: This includes some context-sensitivity in the MVT to LLT conversion so that pointer types are tested correctly. FIXME: I'm not happy with the way this is done since everything is a special-case. I've yet to find a reasonable way to implement it. select-load.mir fails because <1 x s64> loads in tablegen get priority over s64 loads. This is fixed in the next patch and as such they should be committed together, I've posted them separately to help with the review. Depends on D37456 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37457 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315884 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-15[tablegen] Use hasPredCode()/hasImmCode() instead of ↵Daniel Sanders
getPredCode().empty()/getImmCode().empty(). NFC These are cheaper ways of testing for the presence of code than generating the C++ code and testing it's empty. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315872 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-15Re-commit r315863: [globalisel][tablegen] Import ComplexPattern when used as ↵Daniel Sanders
an operator Summary: It's possible for a ComplexPattern to be used as an operator in a match pattern. This is used by the load/store patterns in AArch64 to name the suboperands returned by ComplexPattern predicate so that they can be broken apart and referenced independently in the result pattern. This patch adds support for this in order to enable the import of load/store patterns. Depends on D37445 Hopefully fixed the ambiguous constructor that a large number of bots reported. Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D37456 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315869 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-15Revert r315863: [globalisel][tablegen] Import ComplexPattern when used as an ↵Daniel Sanders
operator A large number of bots are failing on an ambiguous constructor call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315866 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-15[globalisel][tablegen] Import ComplexPattern when used as an operatorDaniel Sanders
Summary: It's possible for a ComplexPattern to be used as an operator in a match pattern. This is used by the load/store patterns in AArch64 to name the suboperands returned by ComplexPattern predicate so that they can be broken apart and referenced independently in the result pattern. This patch adds support for this in order to enable the import of load/store patterns. Depends on D37445 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D37456 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315863 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-15[TableGen] Remove error checks incorrectly failing on non-error conditionsKrzysztof Parzyszek
In type inference, an empty type set for a specific hw mode is not an error. In earlier stages of the design it was, but having to use non- parameterized types with target intrinsics necessarily led to type contradictions: since the intrinsics used specific types, they were only valid for a specific hw mode, and the resulting type set for other modes ended up empty. To accommodate the existence of such intrinsics individual type sets were allowed to be empty as long as not all sets were empty. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315858 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-15Reverting r315590; it did not include changes for llvm-tblgen, which is ↵Aaron Ballman
causing link errors for several people. Error LNK2019 unresolved external symbol "public: void __cdecl `anonymous namespace'::MatchableInfo::dump(void)const " (?dump@MatchableInfo@?A0xf4f1c304@@QEBAXXZ) referenced in function "public: void __cdecl `anonymous namespace'::AsmMatcherEmitter::run(class llvm::raw_ostream &)" (?run@AsmMatcherEmitter@?A0xf4f1c304@@QEAAXAEAVraw_ostream@llvm@@@Z) llvm-tblgen D:\llvm\2017\utils\TableGen\AsmMatcherEmitter.obj 1 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315854 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-15[globalisel][tablegen] Map ld and st to G_LOAD and G_STORE. NFCDaniel Sanders
Summary: There is an important mismatch between ISD::LOAD and G_LOAD (and likewise for ISD::STORE and G_STORE). In SelectionDAG, ISD::LOAD is a non-atomic load and atomic loads are handled by a separate node. However, this is not true of GlobalISel's G_LOAD. For G_LOAD, the MachineMemOperand indicates the atomicity of the operation. As a result, this mapping must also add a predicate that checks for non-atomic MachineMemOperands. This is NFC since these nodes always have predicates in practice and are therefore always rejected at the moment. Depends on D37443 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: kristof.beyls, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37445 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315843 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-15[tablegen] Handle common load/store predicates inside tablegen. NFC.Daniel Sanders
Summary: GlobalISel and SelectionDAG require different code for the common load/store predicates due to differences in the representation. For example: SelectionDAG: (load<signext,i8>:i32 GPR32:$addr) // The <> denote properties of the SDNode that are not printed in the DAG GlobalISel: (G_SEXT:s32 (G_LOAD:s8 GPR32:$addr)) Even without that, differences in the IR (SDNode vs MachineInstr) require differences in the C++ predicate. This patch moves the implementation of the common load/store predicates into tablegen so that it can handle these differences. It's NFC for SelectionDAG since it emits equivalent code and it's NFC for GlobalISel since the rules involving the relevant predicates are still rejected by the importer. Depends on D36618 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Subscribers: llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37443 Includes a partial revert of r315826 since this patch makes it necessary for getPredCode() to return a std::string and getImmCode() should have the same interface as getPredCode(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315841 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-14[TableGen] Avoid unnecessary std::string creationsSimon Pilgrim
Avoid unnecessary std::string creations in the TreePredicateFn getters. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315826 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-14Revert "lit.py: Add new %{shared_output(LABEL)} substitution"Jordan Rose
This reverts r315697 and my ill-fated attempts to fix it on Windows. I'll try again when I get access to a Windows machine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315793 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-17 07:27:12 +0000