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2017-12-05[InstCombine] Don't crash on out of bounds shiftsIgor Laevsky
Differential Revision: https://reviews.llvm.org/D40649 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319761 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-05[X86][AVX512] Tag VPCMP/VPCMPU instruction scheduler classesSimon Pilgrim
Move hardcoded itinerary out to the instruction declarations. Not sure that IIC_SSE_ALU_F32P is the best schedule for integer comparisons, but I'm not going to change it right now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319760 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-05[X86][AVX512] Cleanup VPCMP scheduler classesSimon Pilgrim
Move hardcoded itinerary out to the instruction declarations. Not sure that IIC_SSE_ALU_F32P is the best schedule for integer comparisons, but I'm not going to change it right now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319758 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-05[SystemZ] set 'guessInstructionProperties = 0' and set flags as needed.Jonas Paulsson
This has proven a healthy exercise, as many cases of incorrect instruction flags were corrected in the process. As part of this, IntrWriteMem was added to several SystemZ instrinsics. Furthermore, a bug was exposed in TwoAddress with this change (as incorrect hasSideEffects flags were removed and instructions could now be sunk), and the test case for that bugfix (r319646) is included here as test/CodeGen/SystemZ/twoaddr-sink.ll. One temporary test regression (one extra copy) which will hopefully go away in upcoming patches for similar cases: test/CodeGen/SystemZ/vec-trunc-to-i1.ll Review: Ulrich Weigand. https://reviews.llvm.org/D40437 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319756 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-05[Regalloc] Generate and store multiple regalloc hints.Jonas Paulsson
MachineRegisterInfo used to allow just one regalloc hint per virtual register. This patch extends this to a vector of regalloc hints, which is filled in by common code with sorted copy hints. Such hints will make for more ID copies that can be removed. NB! This improvement is currently (and hopefully temporarily) *disabled* by default, except for SystemZ. The only reason for this is the big impact this has on tests, which has unfortunately proven unmanageable. It was a long while since all the tests were updated and just waiting for review (which didn't happen), but now targets have to enable this themselves instead. Several targets could get a head-start by downloading the tests updates from the Phabricator review. Thanks to those who helped, and sorry you now have to do this step yourselves. This should be an improvement generally for any target! The target may still create its own hint, in which case this has highest priority and is stored first in the vector. If it has target-type, it will not be recomputed, as per the previous behaviour. The temporary hook enableMultipleCopyHints() will be removed as soon as all targets return true. Review: Quentin Colombet, Ulrich Weigand. https://reviews.llvm.org/D38128 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319754 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-05[X86] Fix a bug in handling GRXX subclasses in Domain Reassignment passGuy Blank
When trying to determine the correct Mask register class corresponding to a GPR register class, not all register classes were handled. This caused an assertion to be raised on some scenarios. Differential Revision: https://reviews.llvm.org/D40290 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319745 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-05[X86] Use vector widening to support sign extend from i1 when the dest type ↵Craig Topper
is not 512-bits and vlx is not enabled. Previously we used a wider element type and truncated. But its more efficient to keep the element type and drop unused elements. If BWI isn't supported and we have a i16 or i8 type, we'll extend it to be i32 and still use a truncate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319740 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-05Revert r319691: [globalisel][tablegen] Split atomic load/store into separate ↵Daniel Sanders
opcode and enable for AArch64. Some concerns were raised with the direction. Revert while we discuss it and look into an alternative git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319739 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-05[X86] Fix a crash if avx512bw and xop are both enabled when the IR contrains ↵Craig Topper
a v32i8 bitreverse. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319737 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-05AMDGPU: Fix crash when scheduling DBG_VALUEMatt Arsenault
This calls handleMove with a DBG_VALUE instruction, which isn't tracked by LiveIntervals. I'm not sure this is the correct place to fix this. The generic scheduler seems to have more deliberate region selection that skips dbg_value. The test is also really hard to reduce. I haven't been able to figure out what exactly causes this particular case to try moving the dbg_value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319732 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-05[X86] Use vector widening to support zero extend from i1 when the dest type ↵Craig Topper
is not 512-bits and vlx is not enabled. Previously we used a wider element type and truncated. But its more efficient to keep the element type and drop unused elements. If BWI isn't supported and we have a i16 or i8 type, we'll extend it to be i32 and still use a truncate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319728 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-05[X86] Don't use kunpck for vXi1 concat_vectors if the upper bits are undef.Craig Topper
This can be efficiently selected by a COPY_TO_REGCLASS without the need for an extra instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319726 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-05[X86] Use getZeroVector and remove an unnecessary creation of an APInt ↵Craig Topper
before calling getConstant. NFCI The getConstant function can take care of creating the APInt internally. getZeroVector will take care of using the correct type for the build vector to avoid re-lowering. The test change here is because execution domain constraints apparently pass through undef inputs of a zeroing xor. So the different ordering of register allocation here caused the dependency to change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319725 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instructionJan Vesely
Only used by pre-GCN targets v2: fix predicate setting for FMA_Common Differential Revision: https://reviews.llvm.org/D40692 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319712 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04AMDGPU: Disable fp64 support on pre GCN asicsJan Vesely
It's not implemented. Passing +fp64-fp16-denormal feature enables fp64 even on asics that don't support it v2: fix hasFP64 query Differential Revision: https://reviews.llvm.org/D39931 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319709 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04Revert r319490 "XOR the frame pointer with the stack cookie when protecting ↵Hans Wennborg
the stack" This broke the Chromium build (crbug.com/791714). Reverting while investigating. > Summary: This strengthens the guard and matches MSVC. > > Reviewers: hans, etienneb > > Subscribers: hiraditya, JDevlieghere, vlad.tsyrklevich, llvm-commits > > Differential Revision: https://reviews.llvm.org/D40622 > > git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319490 91177308-0d34-0410-b5e6-96231b3b80d8 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319706 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04AMDGPU: Fix creating invalid copy when adjusting dmaskMatt Arsenault
Move the entire optimization to one place. Before it was possible to adjust dmask without changing the register class of the output instruction, since they were done in separate places. Fix all lane sizes and move all of the optimization into the DAG folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319705 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04Re-submit r289925 (Update .debug_line section version to match DWARF version)Paul Robinson
Set the .debug_line version to match the requested DWARF version, except with a maximum of v4 because we don't support v5 yet. Previously Chromium had issues with this patch; see PR31407. Chromium tool issues have been addressed, so hopefully this will go through this time. Patch by Katya Romanova! Differential Revision: https://reviews.llvm.org/D38002 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319699 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04[globalisel][tablegen] Tests for r319691Daniel Sanders
I forgot to 'svn add' the test files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319698 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04DAG: Match truncated rotation (PR35487)Hans Wennborg
If the truncation has been pushed past the or-node, look through it and truncate afterwards. Differential revision: https://reviews.llvm.org/D40792 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319692 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04[globalisel][tablegen] Split atomic load/store into separate opcode and ↵Daniel Sanders
enable for AArch64. This patch splits atomics out of the generic G_LOAD/G_STORE and into their own G_ATOMIC_LOAD/G_ATOMIC_STORE. This is a pragmatic decision rather than a necessary one. Atomic load/store has little in implementation in common with non-atomic load/store. They tend to be handled very differently throughout the backend. It also has the nice side-effect of slightly improving the common-case performance at ISel since there's no longer a need for an atomicity check in the matcher table. All targets have been updated to remove the atomic load/store check from the G_LOAD/G_STORE path. AArch64 has also been updated to mark G_ATOMIC_LOAD/G_ATOMIC_STORE legal. There is one issue with this patch though which also affects the extending loads and truncating stores. The rules only match when an appropriate G_ANYEXT is present in the MIR. For example, (G_ATOMIC_STORE (G_TRUNC:s16 (G_ANYEXT:s32 (G_ATOMIC_LOAD:s16 X)))) will match but: (G_ATOMIC_STORE (G_ATOMIC_LOAD:s16 X)) will not. This shouldn't be a problem at the moment, but as we get better at eliminating extends/truncates we'll likely start failing to match in some cases. The current plan is to fix this in a patch that changes the representation of extending-load/truncating-store to allow the MMO to describe a different type to the operation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319691 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04Add missing triple args to testsMatthias Braun
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319686 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04[ConstantFold] Support vector index when factoring out GEP index into ↵Haicheng Wu
preceding dimensions Follow-up of r316824. This patch supports the vector type for both current and previous index when factoring out the current one into the previous one. Differential Revision: https://reviews.llvm.org/D39556 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319683 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04[BypassSlowDivision] Improve our handling of divisions by constantsSanjoy Das
(This reapplies r314253. r314253 was reverted on r314482 because of a correctness regression on P100, but that regression was identified to be something else.) Summary: Don't bail out on constant divisors for divisions that can be narrowed without introducing control flow . This gives us a 32 bit multiply instead of an emulated 64 bit multiply in the generated PTX assembly. Reviewers: jlebar Subscribers: jholewinski, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D38265 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319677 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04MachineVerifier: undef phi arg doesn't need to be live-out from predecessorMatthias Braun
Differential Revision: https://reviews.llvm.org/D40756 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319674 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04[CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih
As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319665 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04Fix function pointer tail calls in armv8-M.basePablo Barrio
Summary: The compiler fails with the following error message: fatal error: error in backend: ran out of registers during register allocation Tail call optimization for Armv8-M.base fails to meet all the required constraints when handling calls to function pointers where the arguments take up r0-r3. This is because the pointer to the function to be called can only be stored in r0-r3, but these are all occupied by arguments. This patch makes sure that tail call optimization does not try to handle this type of calls. Reviewers: chill, MatzeB, olista01, rengolin, efriedma Reviewed By: olista01, efriedma Subscribers: efriedma, aemerson, javed.absar, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D40706 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319664 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04[AMDGPU] SDWA: add support for PRESERVE into SDWA peephole.Sam Kolton
Summary: Reviewers: arsenm, vpykhtin, rampitec Subscribers: kzhuravl, wdng, nhaehnle, mgorny, yaxunl, dstuttard, tpr, t-tye Differential Revision: https://reviews.llvm.org/D37817 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319662 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04[ARM] CodeGen testSam Parker
Add another and + load DAG combine test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319660 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04[Loop Predication] Teach LP about reverse loopsAnna Thomas
Summary: Currently, we only support predication for forward loops with step of 1. This patch enables loop predication for reverse or countdownLoops, which satisfy the following conditions: 1. The step of the IV is -1. 2. The loop has a singe latch as B(X) = X <pred> latchLimit with pred as s> or u> 3. The IV of the guard is the decrement IV of the latch condition (Guard is: G(X) = X-1 u< guardLimit). This patch was downstream for a while and is the last series of patches that's from our LP implementation downstream. Reviewers: apilipenko, mkazantsev, sanjoy Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D40353 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319659 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04[NVPTX] Assign valid global namesJonas Hahnfeld
PTX requires that identifiers consist only of [a-zA-Z0-9_$]. The existing pass already ensured this for globals and this patch adds the cleanup for functions with local linkage. However, there was a different problem in the case of collisions of the adjusted name: The ValueSymbolTable then automatically appended ".N" with increasing Ns to get a unique name while helping the ABI demangling. Special case this behavior to omit the dots and append N directly. This will always give us legal names according to the PTX requirements. Differential Revision: https://reviews.llvm.org/D40573 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319657 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04Revert r319649 - [Asm, ARM] Add fallback diag for multiple invalid operandsOliver Stannard
This is causing a failure in the llvm-clang-x86_64-expensive-checks-win buildbot, and I can't reproduce it locally, so reverting until I can work out what is wrong. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319654 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04[Asm, ARM] Add fallback diag for multiple invalid operandsOliver Stannard
This adds a "invalid operands for instruction" diagnostic for instructions where there is an instruction encoding with the correct mnemonic and which is available for this target, but where multiple operands do not match those which were provided. This makes it clear that there is some combination of operands that is valid for the current target, which the default diagnostic of "invalid instruction" does not. Since this is a very general error, we only emit it if we don't have a more specific error. Differential revision: https://reviews.llvm.org/D36747 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319649 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04[AArch64] Allow using emulated tls on platforms other than ELFMartin Storsjo
This matches how it is done on X86. This allows using emulated tls on windows; in MinGW environments, native tls isn't supported at the moment. Set the right Data*bitsDirective for windows to match the existing tests for other platforms. Make parts of the existing tests a regex, to allow matching .section .rdata for windows, to avoid having to duplicate the rest of the tests for windows. Differential Revision: https://reviews.llvm.org/D40770 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319644 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04[ARM] Allow using emulated tls on platforms other than ELFMartin Storsjo
This matches how it is done on X86. This allows using emulated tls on windows; in MinGW environments, native tls isn't supported at the moment. Differential Revision: https://reviews.llvm.org/D40769 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319643 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04[X86] Allow VPMAXUQ/VPMAXSQ/VPMINUQ/VPMINSQ to be used with 128/256 bit ↵Craig Topper
vectors when AVX512 is enabled. These instructions can be used by widening to 512-bits and extracting back to 128/256. We do similar to several other instructions already. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319641 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04[SelectionDAG] Teach computeKnownBits some improvements to ISD::SRL with a ↵Craig Topper
non-splat constant shift amount. If we have a non-splat constant shift amount, the minimum shift amount can be used to infer the number of zero upper bits of the result. There's probably a lot more that we can do here, but this fixes a case where I wanted to infer the sign bit as zero when all the shift amounts are non-zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319639 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-03[X86][AVX512] Tag packed F2I/I2F/F2F conversion instructions scheduler classSimon Pilgrim
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319636 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-03[X86][AVX512] Regenerate schedule tests.Simon Pilgrim
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319635 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-03CodeGen: Fix SelectionDAGISel::LowerArguments for sret addr spaceYaxun Liu
SelectionDAGISel::LowerArguments assumes sret addr space is 0, which is not true for amdgcn---amdgiz target. This patch fixes that. Differential Revision: https://reviews.llvm.org/D40255 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319630 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-03Reland "[WebAssembly] Add visibility flag to Wasm symbol flags""Sam Clegg
Original change was rL319488. This was reverted rL319602 due to a gcc 7.1 warning. Differential Revision: https://reviews.llvm.org/D40772 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319626 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-02CodeGen: Fix pointer info in ↵Yaxun Liu
SplitVecOp_EXTRACT_VECTOR_ELT/SplitVecRes_INSERT_VECTOR_ELT Two issues found when doing codegen for splitting vector with non-zero alloca addr space: DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT/SplitVecOp_EXTRACT_VECTOR_ELT uses dummy pointer info for creating SDStore. Since one pointer operand contains multiply and add, InferPointerInfo is unable to infer the correct pointer info, which ends up with a dummy pointer info for the target to lower store and results in isel failure. The fix is to introduce MachinePointerInfo::getUnknownStack to represent MachinePointerInfo which is known in alloca address space but without other information. TargetLowering::getVectorElementPointer uses value type of pointer in addr space 0 for multiplication of index and then add it to the pointer. However the pointer may be in an addr space which has different size than addr space 0. The fix is to use the pointer value type for index multiplication. Differential Revision: https://reviews.llvm.org/D39758 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319622 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-02[llvm-readobj] Print static MIPS GOTSimon Atanasyan
If a linked binary file contains a dynamic section, the GOT layout defined by the dynamic section entries. In a statically linked file the GOT is just a series of entries. This change teaches `llvm-readobj` to print the GOT in that case. That provides a feature parity with GNU `readelf`. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319616 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-02[X86] Fix copy paste mistake in test case for r319612.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319613 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-02[X86] Teach the assembler to support %db8-%db15 as aliases for %dr8-%dr15.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319612 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-02[X86] Support %dr8-%dr15 in the assembler.Craig Topper
Apparently I failed to make this work when I fixed it in the disassembler way back in r224862. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319611 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-02[ARC] Add instruction subset for the ARC backend.Tatyana Krasnukha
Reviewers: petecoup, kparzysz Reviewed By: petecoup Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37983 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319609 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-02[DAG][AArch64] Disable post-legalization storeNirav Dave
Disable post-legalization store for AArch64 backend which is causing errors out-of-tree. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319607 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-02[WebAssembly] Revert r319488 "Add visibility flag to Wasm symbol flags"Heejin Ahn
This patch reportedly broke one of LLVM bots (ubuntu-gcc7.1-werror). See http://lab.llvm.org:8011/builders/ubuntu-gcc7.1-werror/builds/3369 for details. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319602 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-01Revert "[X86] Improvement in CodeGen instruction selection for LEAs."Matt Morehouse
This reverts r319543, due to ASan bot breakage. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319591 91177308-0d34-0410-b5e6-96231b3b80d8
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