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ampere-computing/llvm.git
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release_70-e8af9b4c407-amp-20181130
LLVM including Ampere Computing toolchain specific patches
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2016-02-15
Implemented stack symbol table ordering/packing optimization to improve data ...
Zia Ansari
2016-02-15
[X86][SSE2] Regenerated sse2 tests
Simon Pilgrim
2016-02-15
[Hexagon] Missed testcase update in r260895
Krzysztof Parzyszek
2016-02-15
[mips] Implemented the .hword directive.
Scott Egerton
2016-02-15
[Hexagon] Use zero-extending loads for anyext
Krzysztof Parzyszek
2016-02-15
[LV] Add support for insertelt/extractelt processing during type truncation
Silviu Baranga
2016-02-15
[X86] More thorough partial-register division checks
Simon Pilgrim
2016-02-15
[X86] Regenerated 64/128 bit multiply tests
Simon Pilgrim
2016-02-15
[X86][SSE] More thorough testing of all-ones vectors re-materialization
Simon Pilgrim
2016-02-15
[X86][SSE] Regenerated uint2fp special case tests
Simon Pilgrim
2016-02-15
Make llvm/test/tools/llvm-symbolizer/pdb/pdb.test Py3-compatible.
NAKAMURA Takumi
2016-02-15
[X86][SSE] Regenerated fast isel intrinsics tests
Simon Pilgrim
2016-02-15
Reverted r260879 as it caused test failures in lld.
Scott Egerton
2016-02-15
[mips] Removed the SHF_ALLOC flag from the .pdr section.
Scott Egerton
2016-02-15
AVX512: Change store size of kmask. Store size of v8i1, v4i1 , v2i1 and i1 ar...
Igor Breger
2016-02-14
[X86][AVX] Fixed copy+paste typo in shuffle test
Simon Pilgrim
2016-02-13
[PM/AA] Wire BasicAA's new pass manager class up to the pass registry.
Chandler Carruth
2016-02-13
[PM/AA] Actually wire the AAManager I built for the new pass manager
Chandler Carruth
2016-02-13
[X86][AVX] Lower shuffles as repeated lane shuffles then lane-crossing shuffles
Simon Pilgrim
2016-02-13
[x86-64] allow mfence even with -mno-sse (PR23203)
Sanjay Patel
2016-02-13
[attrs] Move the norecurse deduction to operate on the node set rather
Chandler Carruth
2016-02-13
AMDGPU: Prepare for reducing private element size.
Matt Arsenault
2016-02-13
AMDGPU/SI: Add llvm.amdgcn.mov.dpp intrinsic
Tom Stellard
2016-02-13
[llvm-size] Make error handling uniform.
Davide Italiano
2016-02-13
AMDGPU: Add intrinsics for sin/cos
Matt Arsenault
2016-02-13
AMDGPU: Rename intrinsic to better match instruction name
Matt Arsenault
2016-02-13
Don't combine fp_round (fp_round x) if f80 to f16 is generated
Pirama Arumuga Nainar
2016-02-12
AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions
Tom Stellard
2016-02-12
Disable the vzeroupper insertion pass on PS4.
Yunzhong Gao
2016-02-12
[Hexagon] Optimize stack slot spills
Krzysztof Parzyszek
2016-02-12
[llvm-pdbdump] Start to decode some streams
David Majnemer
2016-02-12
fix test to use FileCheck
Sanjay Patel
2016-02-12
[codeview] Describe local variables in registers
Reid Kleckner
2016-02-12
[WebAssembly] Fix byval for empty types.
Dan Gohman
2016-02-12
[WebAssembly] Fix insertion of a BLOCK in a loop header that also ends a BLOCK.
Dan Gohman
2016-02-12
[WinEH] Prevent EH state numbering from skipping nested cleanup pads that nev...
Andrew Kaylor
2016-02-12
[LIR] Allow merging of memsets in negatively strided loops.
Chad Rosier
2016-02-12
[SimplifyCFG] Don't fold conditional branches that contain calls to convergen...
Justin Lebar
2016-02-12
[LoopRotate] Don't perform loop rotation if the loop header calls a convergen...
Justin Lebar
2016-02-12
Remove LLVMGetTargetMachineData leftovers.
Benjamin Kramer
2016-02-12
[LVI] Exploit nsw/nuw when computing constant ranges
Philip Reames
2016-02-12
[Hexagon] Replace expansion of spill pseudo-instructions in frame lowering
Krzysztof Parzyszek
2016-02-12
[InstCombine] Don't aggressively replace xor with icmp
David Majnemer
2016-02-12
[AMDGPU] Assembler: Swap operands of flat_store instructions to match AMD ass...
Tom Stellard
2016-02-12
AMDGPU/SI: Annotate Loops with Constant Condition in SIAnnotateControlFlow pass.
Changpeng Fang
2016-02-12
[Hexagon] Eliminate pseudo instructions for circ/brev loads and stores
Krzysztof Parzyszek
2016-02-12
[AArch64] Reduce number of callee-save save/restores.
Geoff Berry
2016-02-12
[AArch64] Add support for Qualcomm Kryo CPU.
Chad Rosier
2016-02-12
[AArch64] Merge two adjacent str WZR into str XZR
Jun Bum Lim
2016-02-12
[Hexagon] Specify vector alignment in DataLayout string
Krzysztof Parzyszek
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