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2017-12-13[PowerPC] MachineSSA pass to reduce the number of CR-logical operationsNemanja Ivanovic
The initial implementation of an MI SSA pass to reduce cr-logical operations. Currently, the only operations handled by the pass are binary operations where both CR-inputs come from the same block and the single use is a conditional branch (also in the same block). Committing this off by default to allow for a period of field testing. Will enable it by default in a follow-up patch soon. Differential Revision: https://reviews.llvm.org/D30431 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320584 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13[X86] Add ENTER/LEAVE schedule testsSimon Pilgrim
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320583 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13[X86] Add IMUL schedule testsSimon Pilgrim
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320582 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13[X86] Add RDMSR/WRMSR, RDPMC + RDTSC/RDTSCP schedule testsSimon Pilgrim
Add missing RDTSCP itinerary git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320581 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13[X86] Add ARPL/BOUND schedule testsSimon Pilgrim
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320580 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13[RISCV] Define sfence.vma InstAliases to match the GNU RISC-V toolsAlex Bradbury
Unfortunately these aren't defined explicitly in the privileged spec, but the GNU assembler does accept `sfence.vma` and `sfence.vma rs` as well as the usual `sfence.vma rs, rt`. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320575 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13[X86][SSE] MOVMSK only uses the sign bit from each vector elementSimon Pilgrim
Pass the input vector through SimplifyDemandedBits as we only need the sign bit from each vector element of MOVMSK We'd probably get more hits if SimplifyDemandedBits was better at handling vectors... Differential Revision: https://reviews.llvm.org/D41119 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320570 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13[RISCV] Implement floating point assembler pseudo instructionsAlex Bradbury
Adds the assembler aliases for the floating point instructions which can be mapped to a single canonical instruction. The missing pseudo instructions (flw, fld, fsw, fsd) are marked as TODO. Other things, like for example PCREL_LO, have to be implemented first. This patch builds upon D40902. Differential Revision: https://reviews.llvm.org/D41071 Patch by Mario Werner. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320569 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13Reintroduce r320049, r320014 and r319894.Igor Laevsky
OpenGL issues should be fixed by now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320568 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13[DAG] Promote ADDCARRY / SUBCARRYRoger Ferrer Ibanez
Add missing case that was not implemented yet. Differential Revision: https://reviews.llvm.org/D38942 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320567 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13[CodeGen] Print jump-table index operands as %jump-table.0 in both MIR and ↵Francis Visoiu Mistrih
debug output Work towards the unification of MIR and debug output by printing `%jump-table.0` instead of `<jt#0>`. Only debug syntax is affected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320566 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13[CodeGen] Print constant pool index operands as %const.0 + 8 in both MIR and ↵Francis Visoiu Mistrih
debug output Work towards the unification of MIR and debug output by printing `%const.0 + 8` instead of `<cp#0+8>` and `%const.0 - 8` instead of `<cp#0-8>`. Only debug syntax is affected. Differential Revision: https://reviews.llvm.org/D41116 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320564 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13[mips] Provide additional DSP bitconvert patternsStefan Maksimovic
Previously, v2i16 -> f32 bitcast could not be matched. Add patterns to support matching this and similar types of bitcasts. Differential revision: https://reviews.llvm.org/D40959 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320562 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13[RISCV] MC layer support for the remaining RVC instructionsAlex Bradbury
Differential Revision: https://reviews.llvm.org/D40003 Patch by Shiva Chen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320558 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13[X86][BMI]: Adding full coverage of MC encoding for the BMI isa set.<NFC>Gadi Haber
NFC. Adding MC regressions tests to cover the BMI1 and BMI2 ISA sets both 32 and 64 bit. This patch is part of a larger task to cover MC encoding of all X86 ISA Sets. started in revision: https://reviews.llvm.org/D39952 Reviewers: zvi, craig.topper, m_zuckerman, RKSimon Differential Revision: https://reviews.llvm.org/D41106 Change-Id: I033ce137b5b82d36e1e601cd5e0534637b43a4a9 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320557 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13Revert "[CGP] Enable select in complex addr mode"Serguei Katkov
Causes: Assertion `ScaledReg == nullptr' failed. This actually a revert of rL320551. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320553 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13[CGP] Enable select in complex addr modeSerguei Katkov
Enable select instruction handling in complex addr modes. Reviewers: john.brawn, reames, aaboud Reviewed By: reames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D40634 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320551 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13[SLP] Vectorize jumbled memory loads.Mohammad Shahid
Summary: This patch tries to vectorize loads of consecutive memory accesses, accessed in non-consecutive or jumbled way. An earlier attempt was made with patch D26905 which was reverted back due to some basic issue with representing the 'use mask' of jumbled accesses. This patch fixes the mask representation by recording the 'use mask' in the usertree entry. Change-Id: I9fe7f5045f065d84c126fa307ef6ebe0787296df Reviewers: mkuper, loladiro, Ayal, zvi, danielcdh Reviewed By: Ayal Subscribers: mgrang, dcaballe, hans, mzolotukhin Differential Revision: https://reviews.llvm.org/D36130 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320548 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13[CallSiteSplitting] Refactor creating callsites.Florian Hahn
Summary: This change makes the call site creation more general if any of the arguments is predicated on a condition in the call site's predecessors. If we find a callsite, that potentially can be split, we collect the set of conditions for the call site's predecessors (currently only 2 predecessors are allowed). To do that, we traverse each predecessor's predecessors as long as it only has single predecessors and record the condition, if it is relevant to the call site. For each condition, we also check if the condition is taken or not. In case it is not taken, we record the inverse predicate. We use the recorded conditions to create the new call sites and split the basic block. This has 2 benefits: (1) it is slightly easier to see what is going on (IMO) and (2) we can easily extend it to handle more complex control flow. Reviewers: davidxl, junbuml Reviewed By: junbuml Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D40728 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320547 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13[hwasan] Inline instrumentation & fixed shadow.Evgeniy Stepanov
Summary: This brings CPU overhead on bzip2 down from 5.5x to 2x. Reviewers: kcc, alekseyshl Subscribers: kubamracek, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D41137 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320538 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13reverting out -r320532 because a warning is breaking the lld buildMichael Trent
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320534 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12Updated llvm-objdump to display local relocations in Mach-O binariesMichael Trent
Summary: llvm-objdump's Mach-O parser was updated in r306037 to display external relocations for MH_KEXT_BUNDLE file types. This change extends the Macho-O parser to display local relocations for MH_PRELOAD files. When used with the -macho option relocations will be displayed in a historical format. rdar://35778019 Reviewers: enderby Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41061 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320532 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12[EarlyCSE] add tests for commuted min/max; NFCSanjay Patel
See PR35642: https://bugs.llvm.org/show_bug.cgi?id=35642 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320530 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12[Hexagon] Relax some checks in testcases, NFCKrzysztof Parzyszek
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320529 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.Alexey Bataev
Summary: If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1, &V2)))), bitcast)`, but the load is used in other instructions, it leads to looping in InstCombiner. Patch adds additional check that all users of the load instructions are stores and then replaces all uses of load instruction by the new one with new type. Reviewers: RKSimon, spatel, majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41072 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320525 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12[Hexagon] Better detection of identity and undef masks in shufflesKrzysztof Parzyszek
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320523 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12[Hexagon] Fix wrong order of operands for vmuxKrzysztof Parzyszek
Shuffle generation uses vmux to collapse vectors resulting from two individual shuffles into one. The indexes of the elements selected from the first operand were indicated by 0xFF in the constant vector used in the compare instruction, but the compare (veqb) set the bits corresponding to the 0x00 elements, thus inverting the selection. Reverse the order of operands to vmux to get the correct output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320516 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12Reassociate: add global reassociation algorithmFiona Glaser
This algorithm (explained more in the source code) takes into account global redundancies by building a "pair map" to find common subexprs. The primary motivation of this is to handle situations like foo = (a * b) * c bar = (a * d) * c where we currently don't identify that "a * c" is redundant. Accordingly, it prioritizes the emission of a * c so that CSE can remove the redundant calculation later. Does not change the actual reassociation algorithm -- only the order in which the reassociated operand chain is reconstructed. Gives ~1.5% floating point math instruction count reduction on a large offline suite of graphics shaders. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320515 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load ↵Alexey Bataev
bitcast." This reverts commit r320510 - again sanitizers bbots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320513 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12Reapply "[X86] Flag BroadWell scheduler model as complete"Sanjoy Das
This reverts commit r320508, in effect re-applying r320308. Simon has already reverted the parts that caused the crash that motivated the revert in r320492. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320512 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12Split IndirectBr critical edges before PGO gen/use passes.Hiroshi Yamauchi
Summary: The PGO gen/use passes currently fail with an assert failure if there's a critical edge whose source is an IndirectBr instruction and that edge needs to be instrumented. To avoid this in certain cases, split IndirectBr critical edges in the PGO gen/use passes. This works for blocks with single indirectbr predecessors, but not for those with multiple indirectbr predecessors (splitting an IndirectBr critical edge isn't always possible.) Reviewers: davidxl, xur Reviewed By: davidxl Subscribers: efriedma, llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D40699 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320511 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.Alexey Bataev
Summary: If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1, &V2)))), bitcast)`, but the load is used in other instructions, it leads to looping in InstCombiner. Patch adds additional check that all users of the load instructions are stores and then replaces all uses of load instruction by the new one with new type. Reviewers: RKSimon, spatel, majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41072 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320510 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12Revert "[X86] Flag BroadWell scheduler model as complete"Sanjoy Das
This reverts commit r320308. r320308 crashes LLC, please see the llvm-commits thread for a reproducer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320508 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12[X86] Cleanup type conversion of 64-bit load-store pairs.Nirav Dave
Summary: Simplify and generalize chain handling and search for 64-bit load-store pairs. Nontemporal test now converts 64-bit integer load-store into f64 which it realizes directly instead of splitting into two i32 pairs. Reviewers: craig.topper, spatel Reviewed By: craig.topper Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D40918 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320505 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12[MachineOperand][MIR] Add isRenamable to MachineOperand.Geoff Berry
Summary: Add isRenamable() predicate to MachineOperand. This predicate can be used by machine passes after register allocation to determine whether it is safe to rename a given register operand. Register operands that aren't marked as renamable may be required to be assigned their current register to satisfy constraints that are not captured by the machine IR (e.g. ABI or ISA constraints). Reviewers: qcolombet, MatzeB, hfinkel Subscribers: nemanjai, mcrosier, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D39400 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320503 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load ↵Alexey Bataev
bitcast." This reverts commit r320499 again to resolve the problem with the sanitizers bbots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320501 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.Alexey Bataev
Summary: If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1, &V2)))), bitcast)`, but the load is used in other instructions, it leads to looping in InstCombiner. Patch adds additional check that all users of the load instructions are stores and then replaces all uses of load instruction by the new one with new type. Reviewers: RKSimon, spatel, majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41072 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320499 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load ↵Alexey Bataev
bitcast." This reverts commit r320496 to solve the problems with sanitizer buildbots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320498 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.Alexey Bataev
Summary: If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1, &V2)))), bitcast)`, but the load is used in other instructions, it leads to looping in InstCombiner. Patch adds additional check that all users of the load instructions are stores and then replaces all uses of load instruction by the new one with new type. Reviewers: RKSimon, spatel, majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41072 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320496 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12[X86] Remove CompleteModel tags from CPU targets until we have better error ↵Simon Pilgrim
checking (PR35636) The checks we have for complete models are not great and miss many cases - e.g. in PR35636 it failed to recognise that only the first output (of 2) was actually tagged by the InstRW Raised PR35639 and PR35643 as examples git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320492 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load ↵Alexey Bataev
bitcast." This reverts commit r320488 because of the failed asan buildbots.. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320490 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.Alexey Bataev
Summary: If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1, &V2)))), bitcast)`, but the load is used in other instructions, it leads to looping in InstCombiner. Patch adds additional check that all users of the load instructions are stores and then replaces all uses of load instruction by the new one with new type. Reviewers: RKSimon, spatel, majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41072 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320488 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12[RISCV] Implement assembler pseudo instructions for RV32I and RV64IAlex Bradbury
Adds the assembler pseudo instructions of RV32I and RV64I which can be mapped to a single canonical instruction. The missing pseudo instructions (e.g., call, tail, ...) are marked as TODO. Other things, like for example PCREL_LO, have to be implemented first. Currently, alias emission is disabled by default to keep the patch minimal. Alias emission by default will be enabled in a subsequent patch which also updates all affected tests. Note that this patch should actually break the floating point MC tests. However, the used FileCheck configuration is not tight enought to detect the breakage. Differential Revision: https://reviews.llvm.org/D40902 Patch by Mario Werner. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320487 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load ↵Alexey Bataev
bitcast." This reverts commit r320483 because of the failed Windows buildbots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320485 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12[RISCV] MC layer support for the instructions added in the privileged specAlex Bradbury
Adds support for the instructions added in the RISC-V privileged ISA (https://content.riscv.org/wp-content/uploads/2017/05/riscv-privileged-v1.10.pdf): uret, sret, mret, wfi, and sfence.vma. Note from the committer: I made very minor formatting changes prior to commit, which didn't seem worth creating another review round-trip for. Differential Revision: https://reviews.llvm.org/D40383 Patch by David Craven. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320484 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.Alexey Bataev
If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1, &V2)))), bitcast)`, but the load is used in other instructions, it leads to looping in InstCombiner. Patch adds additional check that all users of the load instructions are stores and then replaces all uses of load instruction by the new one with new type. Reviewers: RKSimon, spatel, majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41072 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320483 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12[X86] Recognize constant arrays with special values and replace loads from ↵Ayman Musa
it with subtract and shift instructions, which then will be replaced by X86 BZHI machine instruction. Recognize constant arrays with the following values: 0x0, 0x1, 0x3, 0x7, 0xF, 0x1F, .... , 2^(size - 1) -1 where //size// is the size of the array. the result of a load with index //idx// from this array is equivalent to the result of the following: (0xFFFFFFFF >> (sub 32, idx)) (assuming the array of type 32-bit integer). And the result of an 'AND' operation on the returned value of such a load and another input, is exactly equivalent to the X86 BZHI instruction behavior. See test cases in the LIT test for better understanding. Differential Revision: https://reviews.llvm.org/D34141 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320481 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12[InstComineLoadStoreAlloca] Optimize stores to GEP off null baseAnna Thomas
Summary: Currently, in InstCombineLoadStoreAlloca, we have simplification rules for the following cases: 1. load off a null 2. load off a GEP with null base 3. store to a null This patch adds support for the fourth case which is store into a GEP with null base. Since this is UB as well (and directly analogous to the load off a GEP with null base), we can substitute the stored val with undef in instcombine, so that SimplifyCFG can optimize this code into unreachable code. Note: Right now, simplifyCFG hasn't been taught about optimizing this to unreachable and adding an llvm.trap (this is already done for the above 3 cases). Reviewers: majnemer, hfinkel, sanjoy, davide Reviewed by: sanjoy, davide Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41026 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320480 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12[PowerPC] Follow-up to r318436 to get the missed CSE opportunitiesNemanja Ivanovic
The last of the three patches that https://reviews.llvm.org/D40348 was broken up into. Canonicalize the materialization of constants so that they are more likely to be CSE'd regardless of the bit-width of the use. If a constant can be materialized using PPC::LI, materialize it the same way always. For example: li 4, -1 li 4, 255 li 4, 65535 are equivalent if the uses only use the low byte. Canonicalize it to the first form. Differential Revision: https://reviews.llvm.org/D40348 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320473 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12[dsymutil] Accept line tables up to DWARFv5.Jonas Devlieghere
This patch removes the hard-coded check for DWARFv2 line tables. Now dsymutil accepts line tables for DWARF versions 2 to 5 (inclusive). Differential revision: https://reviews.llvm.org/D41084 rdar://35968319 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320469 91177308-0d34-0410-b5e6-96231b3b80d8
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