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AgeCommit message (Expand)Author
2017-12-04[CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih
2017-12-04Fix function pointer tail calls in armv8-M.basePablo Barrio
2017-12-04[AMDGPU] SDWA: add support for PRESERVE into SDWA peephole.Sam Kolton
2017-12-04[ARM] CodeGen testSam Parker
2017-12-04[NVPTX] Assign valid global namesJonas Hahnfeld
2017-12-04[AArch64] Allow using emulated tls on platforms other than ELFMartin Storsjo
2017-12-04[ARM] Allow using emulated tls on platforms other than ELFMartin Storsjo
2017-12-04[X86] Allow VPMAXUQ/VPMAXSQ/VPMINUQ/VPMINSQ to be used with 128/256 bit vecto...Craig Topper
2017-12-04[SelectionDAG] Teach computeKnownBits some improvements to ISD::SRL with a no...Craig Topper
2017-12-03[X86][AVX512] Tag packed F2I/I2F/F2F conversion instructions scheduler classSimon Pilgrim
2017-12-03[X86][AVX512] Regenerate schedule tests.Simon Pilgrim
2017-12-03CodeGen: Fix SelectionDAGISel::LowerArguments for sret addr spaceYaxun Liu
2017-12-02CodeGen: Fix pointer info in SplitVecOp_EXTRACT_VECTOR_ELT/SplitVecRes_INSERT...Yaxun Liu
2017-12-02[DAG][AArch64] Disable post-legalization storeNirav Dave
2017-12-01Revert "[X86] Improvement in CodeGen instruction selection for LEAs."Matt Morehouse
2017-12-01[DAG][ARM] Revert "Reenable post-legalize store merge"Nirav Dave
2017-12-01[opt-remarks] If hotness threshold is set, ignore remarks without hotnessAdam Nemet
2017-12-01Revert "[opt-remarks] If hotness threshold is set, ignore remarks without hot...Adam Nemet
2017-12-01[opt-remarks] If hotness threshold is set, ignore remarks without hotnessAdam Nemet
2017-12-01[ARM] and + load combine testsSam Parker
2017-12-01[ARM][DAG] Reenable post-legalize store mergeNirav Dave
2017-12-01[X86] Improvement in CodeGen instruction selection for LEAs.Jatin Bhateja
2017-12-01[ARM] and + load combine testsSam Parker
2017-12-01[X86][AVX512] Tag vshift/vpermv/pshufd/pshufb instructions scheduler classesSimon Pilgrim
2017-12-01Follow-up to r319434 to turn the pass on by defaultNemanja Ivanovic
2017-12-01[AMDGPU] SiFixSGPRCopies should not modify non-divergent PHIAlexander Timofeev
2017-12-01GlobalISel: Enable the legalization of G_MERGE_VALUES and G_UNMERGE_VALUESVolkan Keles
2017-12-01[X86] Custom legalize v2i32 gathers via widening rather than promoting.Craig Topper
2017-12-01[X86][SelectionDAG] Make sure we explicitly sign extend the index when type p...Craig Topper
2017-12-01[X86] Add another v2i32 gather test case with v2i64 index that wasn't sign ex...Craig Topper
2017-12-01[X86] Add a DAG combine to simplify masks for AVX2 gather instructions.Craig Topper
2017-11-30AMDGPU: Use carry-less adds in FI eliminationMatt Arsenault
2017-11-30AMDGPU: Use gfx9 carry-less add/sub instructionsMatt Arsenault
2017-11-30XOR the frame pointer with the stack cookie when protecting the stackReid Kleckner
2017-11-30[Hexagon] Fix wrong check in test/CodeGen/Hexagon/newvaluejump-solo.mirKrzysztof Parzyszek
2017-11-30[Hexagon] Fix wrong pass in testcaseKrzysztof Parzyszek
2017-11-30[Hexagon] Solo instructions cannot be used with new value jumpsKrzysztof Parzyszek
2017-11-30[X86] Promote i8 CTPOP to i32 instead of i16 when we have the POPCNT instruct...Craig Topper
2017-11-30[aarch64][globalisel] Legalize G_ATOMIC_CMPXCHG_WITH_SUCCESS and G_ATOMICRMW_*Daniel Sanders
2017-11-30[GlobalISel][IRTranslator] Fix crash during translation of zero sized loads/s...Amara Emerson
2017-11-30[globalisel][tablegen] Add support for specific immediates in the match patternDaniel Sanders
2017-11-30[WebAssembly] Revert r319186 "Support bitcasted function addresses with varar...Dan Gohman
2017-11-30[CodeGen] Always use `printReg` to print registers in both MIR and debugFrancis Visoiu Mistrih
2017-11-30[PowerPC] Recommit r314244 with refactoring and off by defaultNemanja Ivanovic
2017-11-30[X86][AVX512] Tag fcmp/ptest/ternlog instructions scheduler classesSimon Pilgrim
2017-11-30[X86][AVX512] Regenerate avx512 schedule testsSimon Pilgrim
2017-11-30[MC] Function stack size section.Sean Eveson
2017-11-30Revert r319423: [MC] Function stack size section.Sean Eveson
2017-11-30[ARM GlobalISel] Bail out for byvalDiana Picus
2017-11-30[CodeGen] Print "%vreg0" as "%0" in both MIR and debug outputFrancis Visoiu Mistrih
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