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path: root/test/CodeGen/X86/vector-shuffle-v1.ll
AgeCommit message (Expand)Author
2018-01-01[X86] In LowerTruncateVecI1, don't add SHL if the input is known to be all si...Craig Topper
2017-12-23[SelectionDAG] Teach SelectionDAG::getNode to constant fold zext/aext/sext of...Craig Topper
2017-12-21[X86] When lowering truncates to vXi1, don't sign extend i16/i8 types to 512-...Craig Topper
2017-12-21[X86] Promote v8i1 shuffles to v8i32 instead of v8i64 if we have VLX.Craig Topper
2017-12-07[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih
2017-12-05[X86] Use vector widening to support sign extend from i1 when the dest type i...Craig Topper
2017-12-04[CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih
2017-11-28[CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih
2017-11-08Revert "Correct dwarf unwind information in function epilogue for X86"Reid Kleckner
2017-11-07Reland "Correct dwarf unwind information in function epilogue for X86"Petar Jovanovic
2017-11-01Revert "Correct dwarf unwind information in function epilogue for X86"Petar Jovanovic
2017-11-01Correct dwarf unwind information in function epilogue for X86Petar Jovanovic
2017-10-10[MC] Suppress .Lcfi labels when emitting textual assemblyReid Kleckner
2017-10-08[X86] getTargetConstantBitsFromNode - add support for decoding scalar constantsSimon Pilgrim
2017-10-08[X86] Stop LowerSIGN_EXTEND_AVX512 from creating v8i16/v16i16/v16i8 vselects ...Craig Topper
2017-09-18[X86] Fix two more places to prefer VPERMQ/PD over VPERM2X128 when AVX2 is en...Craig Topper
2017-09-18[X86] Teach execution domain fixing to convert between VPERMILPS and VPSHUFD.Craig Topper
2017-08-30[AVX512] Use 256-bit extract instructions for extracting bits [255:128] from ...Craig Topper
2017-08-17[AVX512] Don't switch unmasked subvector insert/extract instructions when AVX...Craig Topper
2017-08-03[X86] SET0 to use XMM registers where possible PR26018 PR32862Dinar Temirbulatov
2017-07-31[AVX-512] Remove patterns that select vmovdqu8/16 for unmasked loads. Prefer ...Craig Topper
2017-06-29Revert "r306529 - [X86] Correct dwarf unwind information in function epilogue"Daniel Jasper
2017-06-28[X86] Correct dwarf unwind information in function epiloguePetar Jovanovic
2017-06-21[X86][SSE] Dropped -mcpu from vector shuffle testsSimon Pilgrim
2017-03-28[AVX-512] Fix accidental uses of AH/BH/CH/DH after copies to/from mask registersCraig Topper
2017-03-03[X86] Generate VZEROUPPER for Skylake-avx512.Amjad Aboud
2017-01-09[AVX-512] Add patterns to use a zero masked VPTERNLOG instruction for vselect...Craig Topper
2016-11-30MCStreamer: Use "cfi" for CFI related temp labels.Matthias Braun
2016-11-22[AVX-512] Add support for commuting VPERMT2(B/W/D/Q/PS/PD) to/from VPERMI2(B/...Craig Topper
2016-08-14[AVX512] Fix insertelement i1 lowering.Igor Breger
2016-08-07AVX-512: Changed lowering of BITCAST between i1 vectors and i8/i16/i32 intege...Elena Demikhovsky
2016-07-11[AVX512] Use vpternlog with an immediate of 0xff to create 512-bit all one ve...Craig Topper
2016-07-09VirtRegMap: Replace some identity copies with KILL instructions.Matthias Braun
2016-06-09[X86] Bring consistent naming to the SSE/AVX and AVX512 PALIGNR instructions....Craig Topper
2016-04-03AVX-512: Load and Extended Load for i1 vectorsElena Demikhovsky
2016-02-11[SelectionDAG] change getConstant() to use the input SDLoc when building spla...Sanjay Patel
2016-02-07AVX512: VPBROADCASTB/W/D/Q from GPR intrinsics implementation.Igor Breger
2016-01-28AVX512: Fix truncate v32i8 to v32i1 lowering implementation.Igor Breger
2016-01-21AVX512: Masked move intrinsic implementation.Igor Breger
2016-01-18[X86][AVX2] Broadcast subvectorsSimon Pilgrim
2016-01-18AVX512 : Change v8i1 bitconvert GR8 pattern, remove unnecessary movzbl instru...Igor Breger
2016-01-17[X86][AVX512] Regenerate v1 shuffle testsSimon Pilgrim
2015-12-27AVX512: Change VPMOVB2M DAG lowering , use CVT2MASK node instead TRUNCATE.Igor Breger
2015-10-15AVX512: Implemented DAG lowering for shuff62x2/shufi62x2 instructions ( shuff...Igor Breger
2015-09-17AVX-512: shufflevector for i1 vectors <2 x i1> .. <64 x i1>Elena Demikhovsky
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