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release_70-e8af9b4c407-amp-20181130
LLVM including Ampere Computing toolchain specific patches
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vector-shift-shl-512.ll
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2017-12-04
[CodeGen] Unify MBB reference format in both MIR and debug output
Francis Visoiu Mistrih
2017-09-05
[X86][AVX512] Use AVX512 attributes instead of -mcpu in vector shift tests
Simon Pilgrim
2017-07-31
[AVX-512] Remove patterns that select vmovdqu8/16 for unmasked loads. Prefer ...
Craig Topper
2017-01-24
[X86][SSE] Add support for constant folding vector logical shift by immediates
Simon Pilgrim
2017-01-11
[X86][AVX512BW] Vectorize v64i8 vector shifts
Simon Pilgrim
2017-01-09
[X86][AVX512DQ] Enable v16i16 vector shifts to use an extend+shift+truncate p...
Simon Pilgrim
2017-01-06
[X86][SSE] Standardized triples in vector shift tests
Simon Pilgrim
2017-01-05
[X86] Optimize vector shifts with variable but uniform shift amounts
Zvi Rackover
2016-08-16
[X86][AVX512BW] Updated tests to demonstrate AVX512BW's inability to vectoriz...
Simon Pilgrim
2016-07-21
[X86][SSE] Allow folding of store/zext with PEXTRW of 0'th element
Simon Pilgrim
2016-06-04
[X86][AVX2] Fix v16i16 SHL lowering (PR27730)
Simon Pilgrim
2015-12-23
AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar ...
Igor Breger
2015-11-23
Make utils/update_llc_test_checks.py note that the assertions are
James Y Knight
2015-09-06
[X86][AVX512] Added 512-bit vector shift tests.
Simon Pilgrim