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path: root/test/CodeGen/X86/sse41-schedule.ll
AgeCommit message (Expand)Author
2017-12-12Reapply "[X86] Flag BroadWell scheduler model as complete"Sanjoy Das
2017-12-12Revert "[X86] Flag BroadWell scheduler model as complete"Sanjoy Das
2017-12-10[X86] Flag BroadWell scheduler model as completeSimon Pilgrim
2017-12-08[X86][Haswell]: Updating the scheduling information for the Haswell subtarget.Gadi Haber
2017-12-06[X86][SSE] Regenerate vpmovm2*/vpmov*2m avx512 schedule testsSimon Pilgrim
2017-12-04[CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih
2017-11-13[X86] Use sse_load_f32/f64 in patterns for the memory forms of VRNDSCALESS/SD.Craig Topper
2017-11-13[X86] Use EVEX encoded VRNDSCALE instructions to implement the legacy round i...Craig Topper
2017-11-11[X86] Correct the execution domain on ROUND/VROUND instructions.Craig Topper
2017-11-09Sched model improving on btver2: JFPU01 resource, vtestp* for xmm.Andrew V. Tischenko
2017-10-24[X86][Broadwell] Added the instruction scheduling information for the Broadwe...Gadi Haber
2017-10-23Update DPPD/DPPS instruction scheduling on btver2.Andrew V. Tischenko
2017-10-21[X86][SSE] Add extractps/pextrd equivalence to domain tablesSimon Pilgrim
2017-10-21[X86][SSE] Add missing extractps scheduling testSimon Pilgrim
2017-10-17[X86][Broadwell] Added the broadwell cpu to the scheduling regression tests.<...Gadi Haber
2017-10-17[X86][SKL] Updated scheduling information for the SkylakeClient targetGadi Haber
2017-10-08[X86][SKX] Adding the scheduling information for the SKX target.Gadi Haber
2017-10-06[X86][SSE] Add SKX cpu tests to SSE/AVX scheduling tests (D38443)Simon Pilgrim
2017-09-19[X86][Skylake] Adding the scheduling information for the SkylakeClient targetGadi Haber
2017-08-31AMD family 17h (znver1) scheduler model update.Ashutosh Nema
2017-08-30[X86][Skylake] Fixing duplicated prefixes in the run command of Code Gen regr...Gadi Haber
2017-08-28[X86][Haswell] Updating HSW instruction scheduling informationGadi Haber
2017-08-13[X86][SandyBridge] Additional updates to the SNB instructions scheduling info...Gadi Haber
2017-08-01[X86] Added missing cpu to fix generic scheduling model testsSimon Pilgrim
2017-07-26This patch returns proper value to indicate the case when instruction through...Andrew V. Tischenko
2017-07-19AMD znver1 Initial Scheduler modelCraig Topper
2017-07-10This patch completely replaces the scheduling information for the SandyBridge...Gadi Haber
2017-06-28Reverting commit 306414 on behalf of @gadi.haberMichael Zuckerman
2017-06-27Updated and extended the information about each instruction in HSW and SNB to...Gadi Haber
2017-04-23[X86][SSE] Add scheduling latency/throughput tests for (most) SSE41 instructionsSimon Pilgrim
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