ampere-computing/llvm.git - LLVM including Ampere Computing toolchain specific patches

Age	Commit message (Expand)	Author
2017-12-26	[X86] Pass itins.rr/itins.rm through properly for some instructions.	Craig Topper
2017-12-12	Reapply "[X86] Flag BroadWell scheduler model as complete"	Sanjoy Das
2017-12-12	Revert "[X86] Flag BroadWell scheduler model as complete"	Sanjoy Das
2017-12-10	[X86] Rename some instructions that start with Int_ to have the _Int at the end.	Craig Topper
2017-12-10	[X86] Flag BroadWell scheduler model as complete	Simon Pilgrim
2017-12-10	[X86] Add MOVQI2PQIrm, MOVSDmr, and MOVSDrm to scheduler information	Craig Topper
2017-12-08	[X86][Haswell]: Updating the scheduling information for the Haswell subtarget.	Gadi Haber
2017-12-07	Add proper BTVER2 sched support for MOV instr.	Andrew V. Tischenko
2017-12-07	[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.	Francis Visoiu Mistrih
2017-12-06	[X86][SSE] Regenerate vpmovm2/vpmov2m avx512 schedule tests	Simon Pilgrim
2017-12-04	[CodeGen] Unify MBB reference format in both MIR and debug output	Francis Visoiu Mistrih
2017-11-28	[CodeGen] Print register names in lowercase in both MIR and debug output	Francis Visoiu Mistrih
2017-11-13	[X86][SKX] Adding scheduling info of non-intrinsic + commutable SKX opcodes.	Gadi Haber
2017-11-02	The patch updates sched numbers for YMM AVX instrs such as VMOVx, VORx, VXOR,...	Andrew V. Tischenko
2017-10-30	[X86][SSE] Add clflush scheduling test	Simon Pilgrim
2017-10-24	[X86][Broadwell] Added the instruction scheduling information for the Broadwe...	Gadi Haber
2017-10-17	[X86][Broadwell] Added the broadwell cpu to the scheduling regression tests.<...	Gadi Haber
2017-10-17	[X86][SKL] Updated scheduling information for the SkylakeClient target	Gadi Haber
2017-10-08	[X86][SKX] Adding the scheduling information for the SKX target.	Gadi Haber
2017-10-06	[X86][SSE] Add SKX cpu tests to SSE/AVX scheduling tests (D38443)	Simon Pilgrim
2017-09-19	[X86][Skylake] Adding the scheduling information for the SkylakeClient target	Gadi Haber
2017-09-18	[X86] Teach the execution domain fixing tables to use movlhps inplace of unpc...	Craig Topper
2017-09-18	[X86] Teach execution domain fixing to convert between FP and int unpack inst...	Craig Topper
2017-09-12	[X86] Lower _mm[256\|512]_[mask[z]]_avg_epu[8\|16] intrinsics to native llvm IR	Yael Tsafrir
2017-08-31	AMD family 17h (znver1) scheduler model update.	Ashutosh Nema
2017-08-30	[X86][Skylake] Fixing duplicated prefixes in the run command of Code Gen regr...	Gadi Haber
2017-08-28	[X86][Haswell] Updating HSW instruction scheduling information	Gadi Haber
2017-08-13	[X86][SandyBridge] Additional updates to the SNB instructions scheduling info...	Gadi Haber
2017-08-01	[X86][SSE] Added missing vector logic intrinsic schedules	Simon Pilgrim
2017-08-01	[X86][SSE] Added missing PACKSS/PACKUS intrinsic schedules	Simon Pilgrim
2017-08-01	[X86] Added missing cpu to fix generic scheduling model tests	Simon Pilgrim
2017-08-01	Support itineraries in TargetSubtargetInfo::getSchedInfoStr - Now if the give...	Andrew V. Tischenko
2017-07-19	AMD znver1 Initial Scheduler model	Craig Topper
2017-07-10	This patch completely replaces the scheduling information for the SandyBridge...	Gadi Haber
2017-06-28	Reverting commit 306414 on behalf of @gadi.haber	Michael Zuckerman
2017-06-27	Updated and extended the information about each instruction in HSW and SNB to...	Gadi Haber
2017-04-26	[X86][SSE2] Fix asm string for movq (Move Quadword) instruction.	Ayman Musa
2017-04-23	[X86][SSE] Add missing scheduling latency/throughput test for PINSRW	Simon Pilgrim
2017-04-19	[X86][SSE] Add scheduling latency/throughput tests for (most) SSE2 instructions	Simon Pilgrim