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path: root/test/CodeGen/X86/masked_memop.ll
AgeCommit message (Expand)Author
2017-12-07[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih
2017-12-04[CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih
2017-11-28[CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih
2017-11-16[X86] Update TTI to report that v1iX/v1fX types aren't legal for masked gathe...Craig Topper
2017-11-06[X86][AVX512] Improve lowering of AVX512 test intrinsicsUriel Korach
2017-09-18[X86] Teach the execution domain fixing tables to use movlhps inplace of unpc...Craig Topper
2017-09-18[X86] Teach execution domain fixing to convert between VPERMILPS and VPSHUFD.Craig Topper
2017-09-12[x86] eliminate unnecessary vector compare for AVX masked storeSanjay Patel
2017-09-04[x86] add test for unnecessary cmp + masked store; NFCSanjay Patel
2017-09-03[X86] Add VBLENDPS/VPBLENDD to the execution domain fixing tables.Craig Topper
2017-08-03[X86] SET0 to use XMM registers where possible PR26018 PR32862Dinar Temirbulatov
2017-07-31[AVX-512] Add unmasked subvector inserts and extract to the execution domain ...Craig Topper
2017-07-27[X86] SET0 to use XMM registers where possible PR26018 PR32862Dinar Temirbulatov
2017-06-27Recommitting rL305465 after fixing bug in TableGen in rL306251 & rL306371Ayman Musa
2017-06-15Revert r305465: [X86][AVX512] Improve lowering of AVX512 compare intrinsics (...Simon Pilgrim
2017-06-15[X86][AVX512] Improve lowering of AVX512 compare intrinsics (remove redundant...Ayman Musa
2017-03-28[AVX-512] Fix accidental uses of AH/BH/CH/DH after copies to/from mask registersCraig Topper
2017-03-03[X86] Generate VZEROUPPER for Skylake-avx512.Amjad Aboud
2017-01-14[AVX-512] Teach two address instruction pass to replace masked move instructi...Craig Topper
2017-01-03[AVX-512] Teach EVEX to VEX conversion pass to handle VINSERT and VEXTRACT in...Craig Topper
2016-12-28This is a large patch for X86 AVX-512 of an optimization for reducing code si...Gadi Haber
2016-12-15[x86] use a single shufps when it can save instructionsSanjay Patel
2016-12-15[X86][SSE] Fix domains for scalar store instructionsSimon Pilgrim
2016-12-07[X86][SSE] Consistently set MOVD/MOVQ load/store/move instructions to integer...Simon Pilgrim
2016-09-19[X86 Codegen Test] Divided masked_memop into several files. NFC.Elena Demikhovsky
2016-09-05[AVX-512] Simplify X86InstrInfo::copyPhysReg for 128/256-bit vectors with AVX...Craig Topper
2016-09-04revert r279960. Igor Breger
2016-08-29[AVX512] In some cases KORTEST instruction may be used instead of ZEXT + TEST...Igor Breger
2016-08-25Revert r274613 because it breaks the test suite with AVX512Michael Kuperstein
2016-08-25Revert r279782 due to debug buildbot breakage.Michael Kuperstein
2016-08-25Revert r274613 because it breaks the test suite with AVX512Michael Kuperstein
2016-08-11[AVX512] Fix extractelement i1 lowering.Igor Breger
2016-07-31[AVX512] Add VLX packed move instructions to the execution dependency fix pas...Craig Topper
2016-07-22[AVX512] Add ExeDomain to vector extend and truncate instructions.Craig Topper
2016-07-22[AVX512] Add initial support for the Execution Domain fixing pass to change s...Craig Topper
2016-07-21[X86][SSE] Allow folding of store/zext with PEXTRW of 0'th elementSimon Pilgrim
2016-07-18[X86] Add more opcodes to isFrameLoadOpcode/isFrameStoreOpcode. Mainly AVX-51...Craig Topper
2016-07-18[AVX512] Use VMOVAPSZ128rr/VMOVAPS256rr for VR128X/VR256X physreg moves when ...Craig Topper
2016-07-11[AVX512] Use vpternlog with an immediate of 0xff to create 512-bit all one ve...Craig Topper
2016-07-09VirtRegMap: Replace some identity copies with KILL instructions.Matthias Braun
2016-06-28Support arbitrary addrspace pointers in masked load/store intrinsicsArtur Pilipenko
2016-06-27Revert -r273892 "Support arbitrary addrspace pointers in masked load/store in...Artur Pilipenko
2016-06-27Support arbitrary addrspace pointers in masked load/store intrinsicsArtur Pilipenko
2016-05-21[AVX512] Add patterns for extracting subvectors and storing to memory.Craig Topper
2016-05-21[AVX512] Add patterns for VEXTRACT v16i16->v8i16 and v32i8->v16i8. Disable AV...Craig Topper
2016-05-08[AVX512] Add VLX 128/256-bit SET0 operations that encode to 128/256-bit EVEX ...Craig Topper
2016-04-14Revert "Support arbitrary addrspace pointers in masked load/store intrinsics"Adam Nemet
2016-04-12Support arbitrary addrspace pointers in masked load/store intrinsicsArtur Pilipenko
2016-03-22Revert "Support arbitrary addrspace pointers in masked load/store intrinsics"Matthias Braun
2016-03-14[x86, AVX] replace masked load with full vector load when possibleSanjay Patel
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