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ampere-computing/llvm.git
release_60-f1b37feef3d-amp-20180630
release_70-e8af9b4c407-amp-20181130
LLVM including Ampere Computing toolchain specific patches
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X86
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lea32-schedule.ll
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2017-12-08
[X86][Haswell]: Updating the scheduling information for the Haswell subtarget.
Gadi Haber
2017-12-07
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
Francis Visoiu Mistrih
2017-12-04
[CodeGen] Unify MBB reference format in both MIR and debug output
Francis Visoiu Mistrih
2017-11-28
[CodeGen] Print register names in lowercase in both MIR and debug output
Francis Visoiu Mistrih
2017-10-24
[X86][Broadwell] Added the instruction scheduling information for the Broadwe...
Gadi Haber
2017-10-17
[X86][Broadwell] Added the broadwell cpu to the scheduling regression tests.<...
Gadi Haber
2017-10-17
[X86][SKL] Updated scheduling information for the SkylakeClient target
Gadi Haber
2017-10-10
[X86][SKYLAKE] Update regression test to differentiate between HASWELL and SK...
Gadi Haber
2017-08-31
AMD family 17h (znver1) scheduler model update.
Ashutosh Nema
2017-08-28
[X86][Haswell] Updating HSW instruction scheduling information
Gadi Haber
2017-08-21
[x86] Teach the "generic" x86 CPU to avoid patterns that are slow on
Chandler Carruth
2017-08-01
Support itineraries in TargetSubtargetInfo::getSchedInfoStr - Now if the give...
Andrew V. Tischenko
2017-07-19
AMD znver1 Initial Scheduler model
Craig Topper
2017-07-17
[X86] Add LEA scheduling tests
Simon Pilgrim
