ampere-computing/llvm.git - LLVM including Ampere Computing toolchain specific patches

Age	Commit message (Expand)	Author
2017-12-08	[X86][Haswell]: Updating the scheduling information for the Haswell subtarget.	Gadi Haber
2017-12-04	[CodeGen] Unify MBB reference format in both MIR and debug output	Francis Visoiu Mistrih
2017-10-24	[X86][Broadwell] Added the instruction scheduling information for the Broadwe...	Gadi Haber
2017-10-24	Update f16c instruction scheduling on btver2.	Andrew V. Tischenko
2017-10-23	[X86][F16C] Regenerate F16C schedule tests	Simon Pilgrim
2017-10-17	[X86][Broadwell] Added the broadwell cpu to the scheduling regression tests.<...	Gadi Haber
2017-10-17	[X86][SKL] Updated scheduling information for the SkylakeClient target	Gadi Haber
2017-09-19	[X86][Skylake] Adding the scheduling information for the SkylakeClient target	Gadi Haber
2017-08-31	AMD family 17h (znver1) scheduler model update.	Ashutosh Nema
2017-08-30	[X86][Skylake] Fixing duplicated prefixes in the run command of Code Gen regr...	Gadi Haber
2017-08-28	[X86][Haswell] Updating HSW instruction scheduling information	Gadi Haber
2017-08-01	[X86] Added missing cpu to fix generic scheduling model tests	Simon Pilgrim
2017-07-26	This patch returns proper value to indicate the case when instruction through...	Andrew V. Tischenko
2017-07-19	AMD znver1 Initial Scheduler model	Craig Topper
2017-07-16	[X86] Add F16C scheduling tests	Simon Pilgrim