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path: root/test/CodeGen/RISCV
AgeCommit message (Expand)Author
2017-12-15[RISCV] Enable emission of alias instructions by defaultAlex Bradbury
2017-12-11[RISCV] Add custom CC_RISCV calling convention and improved call supportAlex Bradbury
2017-12-11[RISCV] Allow lowering of dynamic_stackalloc, stacksave, stackrestoreAlex Bradbury
2017-12-11[RISCV] Implement prolog and epilog insertionAlex Bradbury
2017-12-11[RISCV] Support lowering FrameIndexAlex Bradbury
2017-12-04[CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih
2017-11-21[RISCV] Use register X0 (ZERO) for constant 0Alex Bradbury
2017-11-21[RISCV] Support and tests for a variety of additional LLVM IR constructsAlex Bradbury
2017-11-21[RISCV] Implement lowering of ISD::SELECTAlex Bradbury
2017-11-09[RISCV] Re-generate test/CodeGen/RISCV/alu32.ll using update_llc_test_checks.pyAlex Bradbury
2017-11-08[RISCV] Initial support for function callsAlex Bradbury
2017-11-08[RISCV] Codegen for conditional branchesAlex Bradbury
2017-11-08[RISCV] Codegen support for memory operations on global addressesAlex Bradbury
2017-11-08[RISCV] Codegen support for memory operationsAlex Bradbury
2017-11-08[RISCV] Codegen support for materializing constantsAlex Bradbury
2017-10-19[RISCV] Initial codegen support for ALU operationsAlex Bradbury
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