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AgeCommit message (Expand)Author
2018-04-13Merging r329852:Tom Stellard
2018-04-09Merging r327651:Tom Stellard
2018-02-22Merging r325739:Hans Wennborg
2018-01-24Merging r322372 and r322767:Hans Wennborg
2017-12-30[PowerPC] fix a bug in TCO eligibility checkHiroshi Inoue
2017-12-29[PowerPC] Fix for PR35688 - handle out-of-range values for r+r to r+i conversionNemanja Ivanovic
2017-12-28Unbreak test relying on debug output after r321540.Benjamin Kramer
2017-12-22[SelectionDAG] Reverse the order of operands in the ISD::ADD created by Targe...Craig Topper
2017-12-21[PowerPC] Fix parest build failure in SPEC2017.Tony Jiang
2017-12-20[PowerPC] fix a bug in redundant compare eliminationHiroshi Inoue
2017-12-18[PPC] Also disable the pre-emit version of reg+reg to reg+imm transformation.Benjamin Kramer
2017-12-15[PowerPC] Convert r+r instructions to r+i (pre and post RA)Nemanja Ivanovic
2017-12-15Disabling r312514 as it causes miscompiles that show up on bootstrapNemanja Ivanovic
2017-12-14[CodeGen] Print external symbols as $symbol in both MIR and debug outputFrancis Visoiu Mistrih
2017-12-13[PowerPC] MachineSSA pass to reduce the number of CR-logical operationsNemanja Ivanovic
2017-12-12[MachineOperand][MIR] Add isRenamable to MachineOperand.Geoff Berry
2017-12-12[PowerPC] Follow-up to r318436 to get the missed CSE opportunitiesNemanja Ivanovic
2017-12-11[PowerPC] Partially enable the ISEL expansion pass.Tony Jiang
2017-12-11[PowerPC] Sign-extend negative constant storesNemanja Ivanovic
2017-12-07Temporarily revert "[PowerPC] Allow tail calls of fastcc functions from C Cal...Eric Christopher
2017-12-07[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih
2017-12-05Add REQUIRES asserts in combine_loads_from_build_pair.llBjorn Pettersson
2017-12-05[DAGCombine] Handle big endian correctly in CombineConsecutiveLoadsBjorn Pettersson
2017-12-04[CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih
2017-12-01Follow-up to r319434 to turn the pass on by defaultNemanja Ivanovic
2017-11-30[CodeGen] Always use `printReg` to print registers in both MIR and debugFrancis Visoiu Mistrih
2017-11-30[PowerPC] Recommit r314244 with refactoring and off by defaultNemanja Ivanovic
2017-11-30[CodeGen] Print "%vreg0" as "%0" in both MIR and debug outputFrancis Visoiu Mistrih
2017-11-29First step towards more human-friendly PPC assembler output:Joerg Sonnenberger
2017-11-29[Power9] add more tests for D38287; NFCZaara Syeda
2017-11-29[PowerPC] Relax the checking on AND/AND8 in isSignOrZeroExtended.Sean Fertile
2017-11-28[PowerPC] Allow tail calls of fastcc functions from C CallingConv functions.Sean Fertile
2017-11-28[CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih
2017-11-27[PowerPC] Remove redundant TOC savesZaara Syeda
2017-11-27[Power9] Improvements to vector extract with variable index exploitationZaara Syeda
2017-11-20[MachineCSE] Add new callback for is caller preserved or constant physregsTony Jiang
2017-11-20[PPC] Heuristic to choose between a X-Form VSX ld/st vs a X-Form FP ld/st.Tony Jiang
2017-11-16[PPC] Change i32 constant in store instruction to i64Guozhi Wei
2017-11-15[PowerPC] Implement mayBeEmittedAsTailCall for PPCSean Fertile
2017-11-14Rename CountingFunctionInserter and use for both mcount and cygprofile calls,...Hans Wennborg
2017-11-07Use new vector insert half-word and byte instructions when we see inserteleme...Graham Yiu
2017-11-06Adds code to PPC ISEL lowering to recognize byte inserts from vector_shuffles...Graham Yiu
2017-11-06[PPC] Use xxbrd to speed up bswap64Guozhi Wei
2017-11-03[LICM] sink through non-trivially replicable PHIJun Bum Lim
2017-11-01Adds code to PPC ISEL lowering to recognize half-word inserts from vector_shu...Graham Yiu
2017-10-30Revert "[PowerPC] Try to simplify a Swap if it feeds a Splat"Stefan Pintilie
2017-10-30[PPC CodeGen] Fix the bitreverse.i64 intrinsic.Fangrui Song
2017-10-27[DAGCombine] Don't combine sext with extload if sextload is not supported and...Guozhi Wei
2017-10-27Add subclass data to the FoldingSetNode for MemIntrinsicSDNodes.Sean Fertile
2017-10-26Represent runtime preemption in the IR.Sean Fertile
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