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path: root/test/CodeGen/PowerPC/setcc-logic.ll
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2017-12-18[PPC] Also disable the pre-emit version of reg+reg to reg+imm transformation.Benjamin Kramer
This has the same issue as the early pass disabled in r321010. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321013 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-15[PowerPC] Convert r+r instructions to r+i (pre and post RA)Nemanja Ivanovic
This patch adds the necessary infrastructure to convert instructions that take two register operands to those that take a register and immediate if the necessary operand is produced by a load-immediate. Furthermore, it uses this infrastructure to perform such conversions twice - first at MachineSSA and then pre-emit. There are a number of reasons we may end up with opportunities for this transformation, including but not limited to: - X-Form instructions chosen since the exact offset isn't available at ISEL time - Atomic instructions with constant operands (we will add patterns for this in the future) - Tail duplication may duplicate code where one block contains this redundancy - When emitting compare-free code in PPCDAGToDAGISel, we don't handle constant comparands specially Furthermore, this patch moves the initialization of PPCMIPeepholePass so that it can be used for MIR tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320791 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04[CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih
As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319665 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-30[PowerPC] Recommit r314244 with refactoring and off by defaultNemanja Ivanovic
This re-commits everything that was pulled in r314244. The transformation is off by default (patch to enable it to follow). The code is refactored to have a single entry-point and provide fine-grained control over patterns that it selects. This patch also fixes the bugs in the original code. Everything that failed with the original patch has been re-tested with this patch (with the transformation turned on). So the patch to turn this on is soon to follow. Differential Revision: https://reviews.llvm.org/D38575 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319434 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-26[PowerPC] Reverting sequence of patches for elimination of comparison ↵Nemanja Ivanovic
instructions In the past while, I've committed a number of patches in the PowerPC back end aimed at eliminating comparison instructions. However, this causes some failures in proprietary source and these issues are not observed in SPEC or any open source packages I've been able to run. As a result, I'm pulling the entire series and will refactor it to: - Have a single entry point for easy control - Have fine-grained control over which patterns we transform A side-effect of this is that test cases for these patches (and modified by them) are XFAIL-ed. This is a temporary measure as it is counter-productive to remove/modify these test cases and then have to modify them again when the refactored patch is recommitted. The failure will be investigated in parallel to the refactoring effort and the recommit will either have a fix for it or will leave this transformation off by default until the problem is resolved. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314244 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-07[PowerPC] Eliminate integer compare instructions - vol. 3Nemanja Ivanovic
Adds handling for i32 SETNE comparison (both sign and zero extended). Differential Revision: https://reviews.llvm.org/D33718 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304901 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-11[PowerPC] Eliminate integer compare instructions - vol. 1Nemanja Ivanovic
This patch is the first in a series of patches to provide code gen for doing compares in GPRs when the compare result is required in a GPR. It adds the infrastructure to select GPR sequences for i1->i32 and i1->i64 extensions. This first patch handles equality comparison on i32 operands with the result sign or zero extended. Differential Revision: https://reviews.llvm.org/D31847 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302810 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05[DAGCombiner] add and use TLI hook to convert and-of-seteq / or-of-setne to ↵Sanjay Patel
bitwise logic+setcc (PR32401) This is a generic combine enabled via target hook to reduce icmp logic as discussed in: https://bugs.llvm.org/show_bug.cgi?id=32401 It's likely that other targets will want to enable this hook for scalar transforms, and there are probably other patterns that can use bitwise logic to reduce comparisons. Note that we are missing an IR canonicalization for these patterns, and we will probably prefer the pair-of-compares form in IR (shorter, more likely to fold). Differential Revision: https://reviews.llvm.org/D31483 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299542 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-03add/move codegen tests for and/or of setcc; NFCSanjay Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299396 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-01[DAGCombiner] enable vector transforms for any/all {sign} bits set/clearSanjay Patel
The code already allowed vector types in via "isInteger" (which might want a more specific name), so use splat-friendly constant predicates to match those types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299304 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-01[PowerPC, x86] add vector tests for any/all {sign} bits set/clear; NFCSanjay Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299303 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-31[DAGCombiner] add fold for 'All sign bits set?'Sanjay Patel
(and (setlt X, 0), (setlt Y, 0)) --> (setlt (and X, Y), 0) We have 7 similar folds, but this one got away. The fact that the x86 test with a branch didn't change is probably a separate bug. We may also be missing this and the related folds in instcombine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299252 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-31[PowerPC] add tests for setcc+setcc+logic; NFCSanjay Patel
These are the same tests added for x86 with r299238, but PPC doesn't specify all branches as cheap, so we see different patterns in tests with branches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299244 91177308-0d34-0410-b5e6-96231b3b80d8