ampere-computing/llvm.git - LLVM including Ampere Computing toolchain specific patches

Age	Commit message (Collapse)	Author
2017-07-25	[PowerPC] Pretty-print CR bits the way the binutils disassembler does	Nemanja Ivanovic
	This patch just adds printing of CR bit registers in a more human-readable form akin to that used by the GNU binutils. Differential Revision: https://reviews.llvm.org/D31494 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309001 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-13	[PowerPC] Ensure displacements for DQ-Form instructions are multiples of 16	Nemanja Ivanovic
	As outlined in the PR, we didn't ensure that displacements for DQ-Form instructions are multiples of 16. Since the instruction encoding encodes a quad-word displacement, a sub-16 byte displacement is meaningless and ends up being encoded incorrectly. Fixes https://bugs.llvm.org/show_bug.cgi?id=33671. Differential Revision: https://reviews.llvm.org/D35007 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307934 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-24	P9: D-form vector load/store. Differential Revision: ↵	Zaara Syeda
	https://reviews.llvm.org/D33248 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303780 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-02	[PowerPC] Emit VMX loads/stores for aligned ops to avoid adding swaps on LE	Nemanja Ivanovic
	Fixes PR30730. This is a re-commit of a pulled commit. The commit was pulled because some software projects contained uses of Altivec vectors that violated alignment requirements. Known issues have now been fixed. Committing on behalf of Lei Huang. Differential Revision: https://reviews.llvm.org/D26861 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301892 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-29	Revert https://reviews.llvm.org/rL287679	Nemanja Ivanovic
	This commit caused some miscompiles that did not show up on any of the bots. Reverting until we can investigate the cause of those failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288214 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-22	[PowerPC] Emit VMX loads/stores for aligned ops to avoid adding swaps on LE	Nemanja Ivanovic
	This patch corresponds to review: https://reviews.llvm.org/D26861 It also fixes PR30730. Committing on behalf of Lei Huang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287679 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-04	[Power9] Part-word VSX integer scalar loads/stores and sign extend instructions	Nemanja Ivanovic
	This patch corresponds to review: https://reviews.llvm.org/D23155 This patch removes the VSHRC register class (based on D20310) and adds exploitation of the Power9 sub-word integer loads into VSX registers as well as vector sign extensions. The new instructions are useful for a few purposes: Int to Fp conversions of 1 or 2-byte values loaded from memory Building vectors of 1 or 2-byte integers with values loaded from memory Storing individual 1 or 2-byte elements from integer vectors This patch implements all of those uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283190 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-23	[Power9] Exploit move and splat instructions for build_vector improvement	Nemanja Ivanovic
	This patch corresponds to review: https://reviews.llvm.org/D21135 This patch exploits the following instructions: mtvsrws lxvwsx mtvsrdd mfvsrld In order to improve some build_vector and extractelement patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282246 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-22	[Power9] Add exploitation of non-permuting memory ops	Nemanja Ivanovic
	This patch corresponds to review: https://reviews.llvm.org/D19825 The new lxvx/stxvx instructions do not require the swaps to line the elements up correctly. In order to select them over the lxvd2x/lxvw4x instructions which require swaps, the patterns for the old instruction have a predicate that ensures they won't be selected on Power9 and newer CPUs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282143 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-03	Adding -verify-machineinstrs option to PowerPC tests	Ehsan Amiri
	Currently we have a number of tests that fail with -verify-machineinstrs. To detect this cases earlier we add the option to the testcases with the exception of tests that will currently fail with this option. PR 27456 keeps track of this failures. No code review, as discussed with Hal Finkel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277624 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-25	This patch adds support for the vector quadword add/sub instructions introduced	Kit Barton
	in POWER8: vadduqm vaddeuqm vaddcuq vaddecuq vsubuqm vsubeuqm vsubcuq vsubecuq In addition to adding the instructions themselves, it also adds support for the v1i128 type for intrinsics (Intrinsics.td, Function.cpp, and IntrinsicEmitter.cpp). http://reviews.llvm.org/D9081 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238144 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-05	This patch adds ABI support for v1i128 data type.	Kit Barton
	It adds v1i128 to the appropriate register classes and checks parameter passing and return values. This is related to http://reviews.llvm.org/D9081, which will add instructions that exploit the v1i128 datatype. Phabricator review: http://reviews.llvm.org/D9475 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236503 91177308-0d34-0410-b5e6-96231b3b80d8