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path: root/test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll
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2017-11-20[PPC] Heuristic to choose between a X-Form VSX ld/st vs a X-Form FP ld/st.Tony Jiang
The VSX versions have the advantage of a full 64-register target whereas the FP ones have the advantage of lower latency and higher throughput. So what we’re after is using the faster instructions in low register pressure situations and using the larger register file in high register pressure situations. The heuristic chooses between the following 7 pairs of instructions. PPC::LXSSPX vs PPC::LFSX PPC::LXSDX vs PPC::LFDX PPC::STXSSPX vs PPC::STFSX PPC::STXSDX vs PPC::STFDX PPC::LXSIWAX vs PPC::LFIWAX PPC::LXSIWZX vs PPC::LFIWZX PPC::STXSIWX vs PPC::STFIWX Differential Revision: https://reviews.llvm.org/D38486 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318651 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-14[PowerPC] Add codegen for VSX word extract convert to FPLei Huang
Add codegen for VSX word extract conversion from signed/unsigned to single/double precision. For UINT_TO_FP: Extract word unsigned and convert to float was implemented in https://reviews.llvm.org/D20239. Here we will add the missing extract integer and conversion to double. This utilizes the new P9 instruction xxextractuw to extracting an integer element when the result will be converted to double thereby saving 2 direct moves (VSR <-> GPR). For SINT_TO_FP: We will implement the following sequence which will also reduce the number of instructions by saving 2 direct moves. v4i32->f32: xxspltw xvcvsxwsp xscvspdpn v4i32->f64: xxspltw xvcvsxwdp Differential Revision: https://reviews.llvm.org/D35859 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310866 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-24[PowerPC] Fix a performance bug for PPC::XXSLDWI.Tony Jiang
There are some VectorShuffle Nodes in SDAG which can be selected to XXSLDWI instruction, this patch recognizes them and does the selection to improve the PPC performance. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303822 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-24P9: D-form vector load/store. Differential Revision: ↵Zaara Syeda
https://reviews.llvm.org/D33248 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303780 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-09[PPC] Add intrinsics for vector extract word and vector insert word.Sean Fertile
Revision: https://reviews.llvm.org/D26547 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289227 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-22[Power9] Add exploitation of non-permuting memory opsNemanja Ivanovic
This patch corresponds to review: https://reviews.llvm.org/D19825 The new lxvx/stxvx instructions do not require the swaps to line the elements up correctly. In order to select them over the lxvd2x/lxvw4x instructions which require swaps, the patterns for the old instruction have a predicate that ensures they won't be selected on Power9 and newer CPUs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282143 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-14Fix code-gen crash on Power9 for insert_vector_elt with variable index (PR30189)Nemanja Ivanovic
This patch corresponds to review: https://reviews.llvm.org/D24021 In the initial implementation of this instruction, I forgot to account for variable indices. This patch fixes PR30189 and should probably be merged into 3.9.1 (I'll open a bug according to the new instructions). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281479 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-12The test case I added is PowerPC specific but I accidentallyNemanja Ivanovic
had it in the wrong directory. Moved it to CodeGen/PowerPC. Sorry about the noise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275218 91177308-0d34-0410-b5e6-96231b3b80d8
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