path: root/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
AgeCommit message (Collapse)Author
2018-04-14Merging r322373:Tom Stellard
------------------------------------------------------------------------ r322373 | d0k | 2018-01-12 07:03:24 -0800 (Fri, 12 Jan 2018) | 4 lines [PowerPC] Don't miscompile rotate+mask into an ANDIo if it can't recreate the immediate I'm not even sure if this transform is ever worth it, but this at least stops the bleeding. ------------------------------------------------------------------------ git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-13Merging r329852:Tom Stellard
------------------------------------------------------------------------ r329852 | nemanjai | 2018-04-11 14:25:44 -0700 (Wed, 11 Apr 2018) | 8 lines [PowerPC] Fix condition for 64-bit rotate when replacing r+r instr with r+i This patch fixes The condition only covers one of the two 64-bit rotate instructions. This just adds the second (RLDICLo). Patch by Josh Stone. ------------------------------------------------------------------------ git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-29[PowerPC] Fix for PR35688 - handle out-of-range values for r+r to r+i conversionNemanja Ivanovic
Revision 320791 introduced a pass that transforms reg+reg instructions to reg+imm if they're fed by "load immediate". However, it didn't handle out-of-range shifts correctly as reported in PR35688. This patch fixes that and therefore the PR. Furthermore, there was undefined behaviour in the patch where the RHS of an initialization expression was 32 bits and constant `1` was shifted left 32 bits. This was fixed by ensuring the RHS is 64 bits just like the LHS. Differential Revision: git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-15[PowerPC] Convert r+r instructions to r+i (pre and post RA)Nemanja Ivanovic
This patch adds the necessary infrastructure to convert instructions that take two register operands to those that take a register and immediate if the necessary operand is produced by a load-immediate. Furthermore, it uses this infrastructure to perform such conversions twice - first at MachineSSA and then pre-emit. There are a number of reasons we may end up with opportunities for this transformation, including but not limited to: - X-Form instructions chosen since the exact offset isn't available at ISEL time - Atomic instructions with constant operands (we will add patterns for this in the future) - Tail duplication may duplicate code where one block contains this redundancy - When emitting compare-free code in PPCDAGToDAGISel, we don't handle constant comparands specially Furthermore, this patch moves the initialization of PPCMIPeepholePass so that it can be used for MIR tests. git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8