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2016-08-25MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, ↵Matthias Braun
compute it Rename AllVRegsAllocated to NoVRegs. This avoids the connotation of running after register and simply describes that no vregs are used in a machine function. With that we can simply compute the property and do not need to dump/parse it in .mir files. Differential Revision: http://reviews.llvm.org/D23850 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279698 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-24MIRParser/MIRPrinter: Compute HasInlineAsm instead of printing/parsing itMatthias Braun
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279680 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-24MachineRegisterInfo/MIR: Initialize tracksSubRegLiveness early, do not ↵Matthias Braun
print/parser it tracksSubRegLiveness only depends on the Subtarget and a cl::opt, there is not need to change it or save/parse it in a .mir file. Make the field const and move the initialization LiveIntervalAnalysis to the MachineRegisterInfo constructor. Also cleanup some code and fix some instances which better use MachineRegisterInfo::subRegLivenessEnabled() instead of TargetSubtargetInfo::enableSubRegLiveness(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279676 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-24MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.Matthias Braun
Specifying isSSA is an extra line at best and results in invalid MI at worst. Compute the value instead. Differential Revision: http://reviews.llvm.org/D22722 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279600 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-04test: Always treat .mir files as tests even outside of CodeGen/MIRMatthias Braun
We missed a handful of .mir tests that existed outside the test/CodeGen/MIR directory. Also fix the three powerpc .mir tests that nobody noticed were broken. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265350 91177308-0d34-0410-b5e6-96231b3b80d8
2015-08-30[PowerPC/MIR Serialization] Target flags serialization supportHal Finkel
Add support for MIR serialization of PowerPC-specific operand target flags (based on the generic infrastructure added in r244185 and r245383). I won't even pretend that this is good test coverage, but this includes the regression test associated with r246372. Adding an MIR test for that fix is far superior to adding an IR-level test because particular instruction-scheduling decisions are necessary in order to expose the bug, and using an MIR test we can start the pipeline post-scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246373 91177308-0d34-0410-b5e6-96231b3b80d8