| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-10-15 | [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. | Daniel Sanders |
| 2015-04-16 | [opaque pointer type] Add textual IR support for explicit type parameter to t... | David Blaikie |
| 2015-03-13 | [opaque pointer type] Add textual IR support for explicit type parameter to g... | David Blaikie |
| 2015-02-27 | [opaque pointer type] Add textual IR support for explicit type parameter to l... | David Blaikie |
| 2014-06-13 | IR: add "cmpxchg weak" variant to support permitted failure. | Tim Northover |
| 2014-03-11 | IR: add a second ordering operand to cmpxhg for failure | Tim Northover |
| 2013-07-14 | Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to f... | Stephen Lin |
| 2012-10-29 | Expand all atomic ops for mips16. | Reed Kotler |
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index : ampere-computing/llvm.git | |
| LLVM including Ampere Computing toolchain specific patches |
| summaryrefslogtreecommitdiff |