| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2014-07-14 | [mips] Expand BuildPairF64 to a spill and reload when the O32 FPXX ABI is | Sasa Stankovic | |
| enabled and mthc1 and dmtc1 are not available (e.g. on MIPS32r1) This prevents the upper 32-bits of a double precision value from being moved to the FPU with mtc1 to an odd-numbered FPU register. This is necessary to ensure that the code generated executes correctly regardless of the current FPU mode. MIPS32r2 and above continues to use mtc1/mthc1, while MIPS-IV and above continue to use dmtc1. Differential Revision: http://reviews.llvm.org/D4465 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212930 91177308-0d34-0410-b5e6-96231b3b80d8 | |||
| 2014-07-08 | Mips.abiflags is a new implicitly generated section that will be present on ↵ | Vladimir Medic | |
| all new modules. The section contains a versioned data structure which represents essentially information to allow a program loader to determine the requirements of the application. This patch implements mips.abiflags section and provides test cases for it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212519 91177308-0d34-0410-b5e6-96231b3b80d8 | |||
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index : ampere-computing/llvm.git | |
| LLVM including Ampere Computing toolchain specific patches |
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