summaryrefslogtreecommitdiff
path: root/test/CodeGen/MIR
AgeCommit message (Collapse)Author
2017-05-24Move machine-cse-physreg.mir to test/CodeGen/ThumbKrzysztof Parzyszek
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303778 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-24MachineCSE: Respect interblock physreg livenessMikael Holmen
Summary: This is a fix for PR32538. MachineCSE first looks at MO.isDead(), but if it is not marked dead, MachineCSE still wants to do its own check to see if it is trivially dead. This check for the trivial case assumed that physical registers cannot be live out of a block. Patch by Mattias Eriksson. Reviewers: qcolombet, jbhateja Reviewed By: qcolombet, jbhateja Subscribers: jbhateja, llvm-commits Differential Revision: https://reviews.llvm.org/D33408 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303731 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-12[IfConversion] Keep the CFG updated incrementally in IfConvertTriangleMikael Holmen
Summary: Instead of using RemoveExtraEdges (which uses analyzeBranch, which cannot always be trusted) at the end to fixup the CFG we keep the CFG updated as we go along and remove or add branches and merge blocks. This way we won't have any problems if the involved MBBs contain unanalyzable instructions. This fixes PR32721. In that case we had a triangle EBB | \ | | | TBB | / FBB where FBB didn't have any successors at all since it ended with an unconditional return. Then TBB and FBB were be merged into EBB, but EBB would still keep its successors, and the use of analyzeBranch and CorrectExtraCFGEdges wouldn't help to remove them since the return instruction is not analyzable (at least not on ARM). Reviewers: kparzysz, iteratee, MatzeB Reviewed By: iteratee Subscribers: aemerson, rengolin, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33037 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302876 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-10[IfConversion] Add missing check in IfConversion/canFallThroughToMikael Holmen
Summary: When trying to figure out if MBB could fallthrough to ToMBB (possibly by falling through a bunch of other MBBs) we didn't actually check if there was fallthrough between the last two blocks in the chain. Reviewers: kparzysz, iteratee, MatzeB Reviewed By: kparzysz, iteratee Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D32996 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302650 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09Add extra operand to CALLSEQ_START to keep frame part set up previouslySerge Pavlov
Using arguments with attribute inalloca creates problems for verification of machine representation. This attribute instructs the backend that the argument is prepared in stack prior to CALLSEQ_START..CALLSEQ_END sequence (see http://llvm.org/docs/InAlloca.htm for details). Frame size stored in CALLSEQ_START in this case does not count the size of this argument. However CALLSEQ_END still keeps total frame size, as caller can be responsible for cleanup of entire frame. So CALLSEQ_START and CALLSEQ_END keep different frame size and the difference is treated by MachineVerifier as stack error. Currently there is no way to distinguish this case from actual errors. This patch adds additional argument to CALLSEQ_START and its target-specific counterparts to keep size of stack that is set up prior to the call frame sequence. This argument allows MachineVerifier to calculate actual frame size associated with frame setup instruction and correctly process the case of inalloca arguments. The changes made by the patch are: - Frame setup instructions get the second mandatory argument. It affects all targets that use frame pseudo instructions and touched many files although the changes are uniform. - Access to frame properties are implemented using special instructions rather than calls getOperand(N).getImm(). For X86 and ARM such replacement was made previously. - Changes that reflect appearance of additional argument of frame setup instruction. These involve proper instruction initialization and methods that access instruction arguments. - MachineVerifier retrieves frame size using method, which reports sum of frame parts initialized inside frame instruction pair and outside it. The patch implements approach proposed by Quentin Colombet in https://bugs.llvm.org/show_bug.cgi?id=27481#c1. It fixes 9 tests failed with machine verifier enabled and listed in PR27481. Differential Revision: https://reviews.llvm.org/D32394 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302527 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-05Add missing target triple to testMatthias Braun
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302301 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-05MIParser/MIRPrinter: Compute block successors if not explicitely specifiedMatthias Braun
- MIParser: If the successor list is not specified successors will be added based on basic block operands in the block and possible fallthrough. - MIRPrinter: Adds a new `simplify-mir` option, with that option set: Skip printing of block successor lists in cases where the parser is guaranteed to reconstruct it. This means we still print the list if some successor cannot be determined (happens for example for jump tables), if the successor order changes or branch probabilities being unequal. Differential Revision: https://reviews.llvm.org/D31262 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302289 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-01MachineFrameInfo: Track whether MaxCallFrameSize is computed yet; NFCMatthias Braun
This tracks whether MaxCallFrameSize is computed yet. Ideally we would assert and fail when the value is queried before it is computed, however this fails various targets that need to be fixed first. Differential Revision: https://reviews.llvm.org/D32570 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301851 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-11MIR: Allow parsing of empty machine functionsJustin Bogner
If you run llc -stop-after=codegenprepare and feed the resulting MIR to llc -start-after=codegenprepare, you'll have an empty machine function since we haven't run any isel yet. Of course, this only works if the MIRParser believes you that this is okay. This is essentially a revert of r241862 with a fix for the problem it was papering over. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299975 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-03AMDGPU: Remove legacy bfe intrinsicsMatt Arsenault
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299372 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-21AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernelMatt Arsenault
Currently the default C calling convention functions are treated the same as compute kernels. Make this explicit so the default calling convention can be changed to a non-kernel. Converted with perl -pi -e 's/define void/define amdgpu_kernel void/' on the relevant test directories (and undoing in one place that actually wanted a non-kernel). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298444 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-19[MIR] Test assumes x64 windows calling convention upon printing/parsing MIR ↵Oren Ben Simhon
output/input. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298212 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-19[MIR] Add triple to test that assumes it runs on windows.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298211 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-19Moving the test to x86 because other architectures do not suport regcall ↵Oren Ben Simhon
calling convention. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298209 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-19[MIR] Support Customed Register Mask and CSRsOren Ben Simhon
The MIR printer dumps a string that describe the register mask of a function. A static predefined list of register masks matches a static list of strings. However when the register mask is not from the static predefined list, there is no descriptor string and the printer fails. This patch adds support to custom register mask printing and dumping. Also the list of callee saved registers (describing the registers that must be preserved for the caller) might be dynamic. As such this data needs to be dumped and parsed back to the Machine Register Info. Differential Revision: https://reviews.llvm.org/D30971 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298207 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-22MIRTests: Remove unnecessary 2>&1 redirectionMatthias Braun
llc mir output goes to stdout nowadays, so the 2>&1 is not necessary anymore for most tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295859 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-21AMDGPU: Remove dead declarations from MIR testsMatt Arsenault
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295755 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-13MIR: parse & print the atomic parts of a MachineMemOperand.Tim Northover
We're going to need them very soon for GlobalISel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294992 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-20[MIRParser] Allow generic register specification on operand.Ahmed Bougacha
This completes r292321 by adding support for generic registers, e.g.: %2:_(s32) = G_ADD %0, %1 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292550 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-18MIRParser: Allow regclass specification on operandMatthias Braun
You can now define the register class of a virtual register on the operand itself avoiding the need to use a "registers:" block. Example: "%0:gr64 = COPY %rax" Differential Revision: https://reviews.llvm.org/D22398 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292321 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05[AArch64] Fold some filled/spilled subreg COPYsGeoff Berry
Summary: Extend AArch64 foldMemoryOperandImpl() to handle folding spills of subreg COPYs with read-undef defs like: %vreg0:sub_32<def,read-undef> = COPY %WZR; GPR64:%vreg0 by widening the spilled physical source reg and generating: STRXui %XZR <fi#0> as well as folding fills of similar COPYs like: %vreg0:sub_32<def,read-undef> = COPY %vreg1; GPR64:%vreg0, GPR32:%vreg1 by generating: %vreg0:sub_32<def,read-undef> = LDRWui <fi#0> Reviewers: MatzeB, qcolombet Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D27425 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291180 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05CodeGen: Assert that liveness is up to date when reading block live-ins.Matthias Braun
Add an assert that checks whether liveins are up to date before they are used. - Do not print liveins into .mir files anymore in situations where they are out of date anyway. - The assert in the RegisterScavenger is superseded by the new one in livein_begin(). - Skip parts of the liveness updating logic in IfConversion.cpp when liveness isn't tracked anymore (just enough to avoid hitting the new assert()). Differential Revision: https://reviews.llvm.org/D27562 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291169 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22[GlobalISel] More fix for the size vs. type typo. NFC.Quentin Colombet
I missed those in my previous commit (r290378). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290387 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22[MIRParser] Fix a typo in comment and error message.Quentin Colombet
We have long switched from size to type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290378 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-22[MIRParser] Non-generic virtual register may have a type.Quentin Colombet
When generic virtual registers get constrained, because of a use on a target specific operation for instance, we end up with regular virtual registers with a type and that's perfectly fine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290376 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-17Move test to correct directoryMatthias Braun
See also test/CodeGen/MIR/README git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290032 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-10AMDGPU: Fix handling of 16-bit immediatesMatt Arsenault
Since 32-bit instructions with 32-bit input immediate behavior are used to materialize 16-bit constants in 32-bit registers for 16-bit instructions, determining the legality based on the size is incorrect. Change operands to have the size specified in the type. Also adds a workaround for a disassembler bug that produces an immediate MCOperand for an operand that is supposed to be OPERAND_REGISTER. The assembler appears to accept out of bounds immediates and truncates them, but this seems to be an issue for 32-bit already. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289306 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-09Add README describing the intention of test/CodeGen/MIRMatthias Braun
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289265 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-09Move .mir tests to appropriate directoriesMatthias Braun
test/CodeGen/MIR should contain tests that intent to test the MIR printing or parsing. Tests that test something else should be in test/CodeGen/TargetName even when they are written in .mir. As a rule of thumb, only tests using "llc -run-pass none" should be in test/CodeGen/MIR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289254 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-05AMDGPU: Refactor exp instructionsMatt Arsenault
Structure the definitions a bit more like the other classes. The main change here is to split EXP with the done bit set to a separate opcode, so we can set mayLoad = 1 so that it won't be reordered before the other exp stores, since this has the special constraint that if the done bit is set then this should be the last exp in she shader. Previously all exp instructions were inferred to have unmodeled side effects. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288695 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-30AMDGPU: Move mir tests into mir test directoryMatt Arsenault
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288262 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-25AMDGPU/SI: Add back reverted SGPR spilling code, but disable itMarek Olsak
suggested as a better solution by Matt git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287942 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-25Revert "AMDGPU: Implement SGPR spilling with scalar stores"Marek Olsak
This reverts commit 4404d0d6e354e80dd7f8f0a0e12d8ad809cf007e. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287936 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-25Revert "AMDGPU: Make m0 unallocatable"Marek Olsak
This reverts commit 124ad83dae04514f943902446520c859adee0e96. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287932 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-24AMDGPU: Make m0 unallocatableMatt Arsenault
m0 may need to be written for spill code, so we don't want general code uses relying on the value stored in it. This introduces a few code quality regressions where copies from m0 are not coalesced into copies of a copy of m0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287841 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-21[AArch64LoadStoreOptimizer] Don't treat write to XZR/WZR as a clobber.Geoff Berry
Summary: When searching for load/store instructions to pair/merge don't treat writes to WZR/XZR as clobbers since they don't change the value read from WZR/XZR (which is always 0). Reviewers: mcrosier, junbuml, jmolloy, t.p.northover Subscribers: aemerson, llvm-commits, rengolin Differential Revision: https://reviews.llvm.org/D26921 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287592 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-18[MIRPrinter] XFAIL test for powerpcGeoff Berry
This test introduced in r287368 is failing on powerpc for reasons unrelated to branch probabilities. See PR31062. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287375 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-18[MIRPrinter] Print raw branch probabilities as expected by MIRParserGeoff Berry
Fixes PR28751. Reviewers: MatzeB, qcolombet Subscribers: mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D26775 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287368 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-15MIRParser: Add support for parsing vreg reg alloc hintsTom Stellard
Reviewers: qcolombet, MatzeB Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D26573 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286911 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-14RegAllocGreedy: Properly initialize this pass, so that -run-pass will workTom Stellard
Reviewers: qcolombet, MatzeB Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D26572 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286895 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-13AMDGPU: Implement SGPR spilling with scalar storesMatt Arsenault
nThis avoids the nasty problems caused by using memory instructions that read the exec mask while spilling / restoring registers used for control flow masking, but only for VI when these were added. This always uses the scalar stores when enabled currently, but it may be better to still try to spill to a VGPR and use this on the fallback memory path. The cache also needs to be flushed before wave termination if a scalar store is used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286766 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-11AMDGPU/SI: Fix visit order assumption in SIFixSGPRCopiesTom Stellard
Summary: This pass was assuming that when a PHI instruction defined a register used by another PHI instruction that the defining insstruction would be legalized before the using instruction. This assumption was causing the pass to not legalize some PHI nodes within divergent flow-control. This fixes a bug that was uncovered by r285762. Reviewers: nhaehnle, arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D26303 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286676 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-07AMDGPU: Preserve vcc undef flags when inverting branchMatt Arsenault
If the branch was on a read-undef of vcc, passes that used analyzeBranch to invert the branch condition wouldn't preserve the undef flag resulting in a verifier error. Fixes verifier failures in a future commit. Also fix verifier error when inserting copy for vccz corruption bug. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286133 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-02AMDGPU: Allow additional implicit operands on MOVRELS instructionsNicolai Haehnle
Summary: The post-RA scheduler occasionally uses additional implicit operands when the vector implicit operand as a whole is killed, but some subregisters are still live because they are directly referenced later. Unfortunately, this seems incredibly subtle to reproduce. Fixes piglit spec/glsl-110/execution/variable-indexing/vs-temp-array-mat2-index-wr.shader_test and others. Reviewers: arsenm, tstellarAMD Subscribers: kzhuravl, wdng, yaxunl, tony-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D25656 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285835 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-28AMDGPU/SI: Don't use non-0 waitcnt values when waiting on Flat instructionsTom Stellard
Summary: Flat instruction can return out of order, so we need always need to wait for all the outstanding flat operations. Reviewers: tony-tye, arsenm Subscribers: kzhuravl, wdng, nhaehnle, llvm-commits, yaxunl Differential Revision: https://reviews.llvm.org/D25998 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285479 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-28AMDGPU: Add definitions for scalar store instructionsMatt Arsenault
Also add glc bit to the scalar loads since they exist on VI and change the caching behavior. This currently has an assembler bug where the glc bit is incorrectly accepted on SI/CI which do not have it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285463 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-27AMDGPU/SI: Handle hazard with s_rfe_b64Tom Stellard
Reviewers: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye Differential Revision: https://reviews.llvm.org/D25638 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285368 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-27AMDGPU/SI: Handle hazard with sgpr lane selects for v_{read,write}laneTom Stellard
Reviewers: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D25637 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285367 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-27AMDGPU/SI: Handle hazard with > 8 byte VMEM storesTom Stellard
Reviewers: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D25577 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285359 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-27AMDGPU/SI: Handle s_setreg hazard in GCNHazardRecognizerTom Stellard
Reviewers: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye Differential Revision: https://reviews.llvm.org/D25528 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285338 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-19 19:25:25 +0000