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path: root/test/CodeGen/MIR
AgeCommit message (Expand)Author
2017-05-24Move machine-cse-physreg.mir to test/CodeGen/ThumbKrzysztof Parzyszek
2017-05-24MachineCSE: Respect interblock physreg livenessMikael Holmen
2017-05-12[IfConversion] Keep the CFG updated incrementally in IfConvertTriangleMikael Holmen
2017-05-10[IfConversion] Add missing check in IfConversion/canFallThroughToMikael Holmen
2017-05-09Add extra operand to CALLSEQ_START to keep frame part set up previouslySerge Pavlov
2017-05-05Add missing target triple to testMatthias Braun
2017-05-05MIParser/MIRPrinter: Compute block successors if not explicitely specifiedMatthias Braun
2017-05-01MachineFrameInfo: Track whether MaxCallFrameSize is computed yet; NFCMatthias Braun
2017-04-11MIR: Allow parsing of empty machine functionsJustin Bogner
2017-04-03AMDGPU: Remove legacy bfe intrinsicsMatt Arsenault
2017-03-21AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernelMatt Arsenault
2017-03-19[MIR] Test assumes x64 windows calling convention upon printing/parsing MIR o...Oren Ben Simhon
2017-03-19[MIR] Add triple to test that assumes it runs on windows.Benjamin Kramer
2017-03-19Moving the test to x86 because other architectures do not suport regcall call...Oren Ben Simhon
2017-03-19[MIR] Support Customed Register Mask and CSRsOren Ben Simhon
2017-02-22MIRTests: Remove unnecessary 2>&1 redirectionMatthias Braun
2017-02-21AMDGPU: Remove dead declarations from MIR testsMatt Arsenault
2017-02-13MIR: parse & print the atomic parts of a MachineMemOperand.Tim Northover
2017-01-20[MIRParser] Allow generic register specification on operand.Ahmed Bougacha
2017-01-18MIRParser: Allow regclass specification on operandMatthias Braun
2017-01-05[AArch64] Fold some filled/spilled subreg COPYsGeoff Berry
2017-01-05CodeGen: Assert that liveness is up to date when reading block live-ins.Matthias Braun
2016-12-22[GlobalISel] More fix for the size vs. type typo. NFC.Quentin Colombet
2016-12-22[MIRParser] Fix a typo in comment and error message.Quentin Colombet
2016-12-22[MIRParser] Non-generic virtual register may have a type.Quentin Colombet
2016-12-17Move test to correct directoryMatthias Braun
2016-12-10AMDGPU: Fix handling of 16-bit immediatesMatt Arsenault
2016-12-09Add README describing the intention of test/CodeGen/MIRMatthias Braun
2016-12-09Move .mir tests to appropriate directoriesMatthias Braun
2016-12-05AMDGPU: Refactor exp instructionsMatt Arsenault
2016-11-30AMDGPU: Move mir tests into mir test directoryMatt Arsenault
2016-11-25AMDGPU/SI: Add back reverted SGPR spilling code, but disable itMarek Olsak
2016-11-25Revert "AMDGPU: Implement SGPR spilling with scalar stores"Marek Olsak
2016-11-25Revert "AMDGPU: Make m0 unallocatable"Marek Olsak
2016-11-24AMDGPU: Make m0 unallocatableMatt Arsenault
2016-11-21[AArch64LoadStoreOptimizer] Don't treat write to XZR/WZR as a clobber.Geoff Berry
2016-11-18[MIRPrinter] XFAIL test for powerpcGeoff Berry
2016-11-18[MIRPrinter] Print raw branch probabilities as expected by MIRParserGeoff Berry
2016-11-15MIRParser: Add support for parsing vreg reg alloc hintsTom Stellard
2016-11-14RegAllocGreedy: Properly initialize this pass, so that -run-pass will workTom Stellard
2016-11-13AMDGPU: Implement SGPR spilling with scalar storesMatt Arsenault
2016-11-11AMDGPU/SI: Fix visit order assumption in SIFixSGPRCopiesTom Stellard
2016-11-07AMDGPU: Preserve vcc undef flags when inverting branchMatt Arsenault
2016-11-02AMDGPU: Allow additional implicit operands on MOVRELS instructionsNicolai Haehnle
2016-10-28AMDGPU/SI: Don't use non-0 waitcnt values when waiting on Flat instructionsTom Stellard
2016-10-28AMDGPU: Add definitions for scalar store instructionsMatt Arsenault
2016-10-27AMDGPU/SI: Handle hazard with s_rfe_b64Tom Stellard
2016-10-27AMDGPU/SI: Handle hazard with sgpr lane selects for v_{read,write}laneTom Stellard
2016-10-27AMDGPU/SI: Handle hazard with > 8 byte VMEM storesTom Stellard
2016-10-27AMDGPU/SI: Handle s_setreg hazard in GCNHazardRecognizerTom Stellard
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