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2018-01-02[Hexagon] Fix generation of vector sign extensionsKrzysztof Parzyszek
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321650 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-20[Hexagon] Allow construction of HVX vector predicatesKrzysztof Parzyszek
Handle BUILD_VECTOR of boolean values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321220 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-20[Hexagon] Adjust the value type for BCvt in LowerFormalArgumentsKrzysztof Parzyszek
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321177 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-18[Hexagon] Cache loads to select to avoid traversing mutating DAGKrzysztof Parzyszek
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321034 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-18[Hexagon] Generate HVX code for vector sign-, zero- and any-extendsKrzysztof Parzyszek
Implement any-extend as zero-extend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321004 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-15[Hexagon] Handle concat_vectors of all allowed HVX typesKrzysztof Parzyszek
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320865 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-15[Hexagon] Fix operand-swapping PatFrag for atomic storesKrzysztof Parzyszek
PatFrag now has the atomicity information stored as bit fields. They need to be copied to the new PatFrag. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320855 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14[Hexagon] Generate HVX code for comparisons and selectsKrzysztof Parzyszek
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320744 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12[Hexagon] Relax some checks in testcases, NFCKrzysztof Parzyszek
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320529 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12[Hexagon] Better detection of identity and undef masks in shufflesKrzysztof Parzyszek
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320523 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12[Hexagon] Fix wrong order of operands for vmuxKrzysztof Parzyszek
Shuffle generation uses vmux to collapse vectors resulting from two individual shuffles into one. The indexes of the elements selected from the first operand were indicated by 0xFF in the constant vector used in the compare instruction, but the compare (veqb) set the bits corresponding to the 0x00 elements, thus inverting the selection. Reverse the order of operands to vmux to get the correct output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320516 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12[MachineOperand][MIR] Add isRenamable to MachineOperand.Geoff Berry
Summary: Add isRenamable() predicate to MachineOperand. This predicate can be used by machine passes after register allocation to determine whether it is safe to rename a given register operand. Register operands that aren't marked as renamable may be required to be assigned their current register to satisfy constraints that are not captured by the machine IR (e.g. ABI or ISA constraints). Reviewers: qcolombet, MatzeB, hfinkel Subscribers: nemanjai, mcrosier, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D39400 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320503 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-11[Hexagon] Add support for Hexagon V65Krzysztof Parzyszek
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320404 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-11[Hexagon] Crash in instruction selection for insert_vector_elt for HVXKrzysztof Parzyszek
A wrong type was passed to insertVector, causing an out-of-bounds value to be added an an operand to HexagonISD::INSERT. This later failed in instruction selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320369 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-07[Hexagon] Generate HVX code for basic arithmetic operationsKrzysztof Parzyszek
Handle and, or, xor, add, sub, mul for vectors of i8, i16, and i32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320063 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-07[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih
Work towards the unification of MIR and debug output by refactoring the interfaces. For MachineOperand::print, keep a simple version that can be easily called from `dump()`, and a more complex one which will be called from both the MIRPrinter and MachineInstr::print. Add extra checks inside MachineOperand for detached operands (operands with getParent() == nullptr). https://reviews.llvm.org/D40836 * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: ([^ ]+) ([^ ]+)<def> ([^ ]+)/kill: \1 def \2 \3/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: ([^ ]+) ([^ ]+) ([^ ]+)<def>/kill: \1 \2 def \3/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: def ([^ ]+) ([^ ]+) ([^ ]+)<def>/kill: def \1 \2 def \3/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/<def>//g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<kill>/killed \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-use,kill>/implicit killed \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<dead>/dead \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<def[ ]*,[ ]*dead>/dead \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-def[ ]*,[ ]*dead>/implicit-def dead \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-def>/implicit-def \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-use>/implicit \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<internal>/internal \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<undef>/undef \1/g' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320022 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-06[Hexagon] Recognize vdealb, vdealh, vshuffb and vshuffh specificallyKrzysztof Parzyszek
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319978 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-06[Hexagon] Handle perfect shuffles on single vectorsKrzysztof Parzyszek
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319965 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-06[Hexagon] Generate HVX code for vector construction and accessKrzysztof Parzyszek
Support for: - build vector, - extract vector element, subvector, - insert vector element, subvector, - shuffle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319901 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04[CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih
As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319665 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-30[Hexagon] Fix wrong check in test/CodeGen/Hexagon/newvaluejump-solo.mirKrzysztof Parzyszek
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319476 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-30[Hexagon] Fix wrong pass in testcaseKrzysztof Parzyszek
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319471 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-30[Hexagon] Solo instructions cannot be used with new value jumpsKrzysztof Parzyszek
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319470 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-30[CodeGen] Always use `printReg` to print registers in both MIR and debugFrancis Visoiu Mistrih
output As part of the unification of the debug format and the MIR format, always use `printReg` to print all kinds of registers. Updated the tests using '_' instead of '%noreg' until we decide which one we want to be the default one. Differential Revision: https://reviews.llvm.org/D40421 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319445 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-30[CodeGen] Print "%vreg0" as "%0" in both MIR and debug outputFrancis Visoiu Mistrih
As part of the unification of the debug format and the MIR format, avoid printing "vreg" for virtual registers (which is one of the current MIR possibilities). Basically: * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g" * grep -nr '%vreg' . and fix if needed * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g" * grep -nr 'vreg[0-9]\+' . and fix if needed Differential Revision: https://reviews.llvm.org/D40420 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319427 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29[Hexagon] Remove HexagonISD::PACKHLKrzysztof Parzyszek
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319352 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-28[Hexagon] Make sure to zero-extend bytes before building a vectorKrzysztof Parzyszek
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319204 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-22[Hexagon] Implement buildVector32 and buildVector64 as utility functionsKrzysztof Parzyszek
Change LowerBUILD_VECTOR to use those functions. This commit will tempora- rily affect constant vector generation (it will generate constant-extended values instead of non-extended combines), but the code for the general case should be better. The constant selection part will be fixed later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318877 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-22[Hexagon] Add patterns to select A2_combine_ll and its variantsKrzysztof Parzyszek
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318876 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-22[Hexagon] Remove trailing spaces, NFCKrzysztof Parzyszek
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318875 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-21[Hexagon] Make sure that RDF does not remove EH_LABELsKrzysztof Parzyszek
Since EH_LABELs (and other labels) no longer have "side-effects", they should be checked for separately. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318801 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-02[Hexagon] Prefer L2_loadrub_io over L4_loadrub_rrKrzysztof Parzyszek
If the offset is an immediate, avoid putting it in a register to get Rs+Rt<<#0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317275 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-27[Hexagon] Adjust patterns to reflect instruction selection preferencesKrzysztof Parzyszek
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316804 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-27[Hexagon] Fix an incorrect assertion in HexagonConstExtenders.cppKrzysztof Parzyszek
Making sure that an instruction has fewer operands than required, then attempting to access one out of range is going to fail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316785 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-25[Hexagon] Account for negative offset when limiting max deviationKrzysztof Parzyszek
In getOffsetRange, Max can be set to 0 to force the extender replacement to be at or below the original value. This would cause the new offset to be non-negative, which is preferred for memory instructions (to reduce the likelihood of it getting constant-extended due to predication). The problem happens when the range is shifted by an offset (present in the instruction being examined) and the offset is negative. The entire range for the allowable deviation will then be strictly negative. This creates a problem, since 0 is assumed to be a valid deviation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316601 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-24MIR: Print the register class or bank in vreg defsJustin Bogner
This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316479 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-23[Hexagon] Return the correct chain edge for i1 function callsKrzysztof Parzyszek
In HexagonISelLowering, there is code to handle the case when a function returns an i1 type. In this case, we need to generate extra nodes to copy the result from R0 to a predicate register. The code was returning the wrong value for the chain edge which caused an assert "Wrong topological sorting" when converting the instructions to MIs. This patch fixes the problem by returning the chain for the final copy. Patch by Brendon Cahoon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316367 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-23[Hexagon] Add extra pattern for S4_addaddiKrzysztof Parzyszek
One combination was missing: add(add(x,y),c). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316363 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-20[Packetizer] Add function to check for aliasing between instructionsKrzysztof Parzyszek
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316243 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-20[Hexagon] Report error instead of crashing on wrong inline-asm constraintsKrzysztof Parzyszek
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316236 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-20[Hexagon] Reorganize and update instruction patternsKrzysztof Parzyszek
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316228 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-20[Hexagon] Allow redefinition with immediates for hw loop conversionKrzysztof Parzyszek
Normally, if the registers holding the induction variable's bounds are redefined inside of the loop's body, the loop cannot be converted to a hardware loop. However, if the redefining instruction is actually loading an immediate value into the register, this conversion is both possible and legal (since the immediate itself will be used in the loop setup in the preheader). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316218 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-19[Hexagon] Fix store conversion from rr to io in optimize addressing modesKrzysztof Parzyszek
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316170 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-18[Hexagon] New HVX target features.Sumanth Gundapaneni
This patch lets the llvm tools handle the new HVX target features that are added by frontend (clang). The target-features are of the form "hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX. "hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated. The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}. Eg: "+hvxv62" For the correct HVX code generation, the user must use the following target features. For 64B mode: "+hvxv62" "+hvx-length64b" For 128B mode: "+hvxv62" "+hvx-length128b" Clang picks a default length if none is specified. If for some reason, no hvx-length is specified to llvm, the compilation will bail out. There is a corresponding clang patch. Differential Revision: https://reviews.llvm.org/D38851 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316101 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-13[Hexagon] Minimize number of repeated constant extendersKrzysztof Parzyszek
Each constant extender requires an extra instruction, which adds to the code size and also reduces the number of available slots in an instruction packet. In most cases, the value of a repeated constant extender could be loaded into a register, and the instructions using the extender could be replaced with their counterparts that use that register instead. This patch adds a pass that tries to reduce the number of constant extenders, including extenders which differ only in an immediate offset known at compile time, e.g. @global and @global+12. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315735 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-13[Hexagon] Add patterns for cmpb/cmph with immediate argumentsKrzysztof Parzyszek
Patch by Sumanth Gundapaneni. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315692 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-11[Hexagon] Make sure that new-value jump is packetized with producerKrzysztof Parzyszek
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315510 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-11[Pipeliner] Improve serialization order for post-incrementsKrzysztof Parzyszek
The pipeliner is generating a serial sequence that causes poor register allocation when a post-increment instruction appears prior to the use of the post-increment register. This occurs when there is a circular set of dependences involved with a sequence of instructions in the same cycle. In this case, there is no serialization of the parallel semantics that will not cause an additional register to be allocated. This patch fixes the problem by changing the instructions so that the post-increment instruction is used by the subsequent instruction, which enables the register allocator to make a better decision and not require another register. Patch by Brendon Cahoon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315466 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-02[Hexagon] Check vector elements for equivalence in the ↵Ron Lieberman
HexagonVectorLoopCarriedReuse pass If the two instructions being compared for equivalence have corresponding operands that are integer constants, then check their values to determine equivalence. Patch by Suyog Sarda! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314642 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-02[Hexagon] Patch to Extract i1 element from vector of i1Ron Lieberman
This patch extracts 1 element from vector consisting of elements of size 1 bit at given index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314641 91177308-0d34-0410-b5e6-96231b3b80d8
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