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Improve ReduceLoadWidth for SRL Patch is causing an issue on the
PPC64 BE santizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321349 91177308-0d34-0410-b5e6-96231b3b80d8
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If the SRL node is only used by an AND, we may be able to set the
ExtVT to the width of the mask, making the AND redundant. To support
this, another check has been added in isLegalNarrowLoad which queries
whether the load is valid.
Differential Revision: https://reviews.llvm.org/D41350
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321259 91177308-0d34-0410-b5e6-96231b3b80d8
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Correct the CHECK-LABELS of a couple of dag combine tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320963 91177308-0d34-0410-b5e6-96231b3b80d8
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Add some more and and shift load combine tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320822 91177308-0d34-0410-b5e6-96231b3b80d8
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Change the calculation for the desired ValueType for non-sign
extending loads, as in those cases we don't care about the
higher bits. This creates a smaller ExtVT and allows for such
combinations as:
(srl (zextload i16, [addr]), 8) -> (zextload i8, [addr + 1])
Differential Revision: https://reviews.llvm.org/D40034
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318390 91177308-0d34-0410-b5e6-96231b3b80d8
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1.Fix pessimized case in FIXME.
2.Add tests for it.
3.The canonicalisation on shifts results in different sequence for
tests of machine-licm.Correct some check lines.
Differential Revision: https://reviews.llvm.org/D27916
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290410 91177308-0d34-0410-b5e6-96231b3b80d8
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