| Age | Commit message (Expand) | Author |
|---|
| 2017-11-27 | [DAG] Do MergeConsecutiveStores again before Instruction Selection | Nirav Dave |
| 2017-11-27 | [AMDGPU] Add custom lowering for llvm.log{,10}.{f16,f32} intrinsics | Vedran Miletic |
| 2017-11-22 | [AMDGPU] Fix SITargetLowering::LowerCall for pointer info of byval argument | Yaxun Liu |
| 2017-11-22 | AMDGPU: Consider memory dependencies with moved instructions in SILoadStoreOp... | Nicolai Haehnle |
| 2017-11-21 | [AMDGPU] Fix DAGTypeLegalizer::SplitInteger for shift amount type | Yaxun Liu |
| 2017-11-20 | [AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/su... | Dmitry Preobrazhensky |
| 2017-11-20 | [AMDGPU] Update test r600.amdgpu-alias-analysis.ll | Yaxun Liu |
| 2017-11-20 | AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experi... | Valery Pykhtin |
| 2017-11-17 | AMDGPU: Move hazard avoidance out of waitcnt pass. | Matt Arsenault |
| 2017-11-17 | [AMDGPU][MC][GFX9][disassembler] Corrected decoding of op_sel_hi for v_mad_mix* | Dmitry Preobrazhensky |
| 2017-11-17 | AMDGPU: Fix breaking SMEM clauses | Matt Arsenault |
| 2017-11-16 | Let llvm.invariant.group.barrier accepts pointer to any address space | Yaxun Liu |
| 2017-11-16 | Fix pointer EVT in SelectionDAGBuilder::visitAlloca | Yaxun Liu |
| 2017-11-16 | Fix APInt bit size in processDbgDeclares | Yaxun Liu |
| 2017-11-15 | AMDGPU: Replace i64 add/sub lowering | Matt Arsenault |
| 2017-11-15 | AMDGPU: Don't use MUBUF vaddr if address may overflow | Matt Arsenault |
| 2017-11-14 | AMDGPU: Handle or in multi-use shl ptr combine | Matt Arsenault |
| 2017-11-14 | [AMDGPU] updated PAL metadata record keys | Tim Renouf |
| 2017-11-14 | [GISel]: Rework legalization algorithm for better elimination of | Aditya Nandakumar |
| 2017-11-14 | AMDGPU: Error on stack size overflow | Matt Arsenault |
| 2017-11-14 | CodeGen: Fix TargetLowering::LowerCallTo for sret value type | Yaxun Liu |
| 2017-11-14 | AMDGPU: Fix test | Matt Arsenault |
| 2017-11-14 | AMDGPU: Fix producing saveexec when the copy is spilled | Matt Arsenault |
| 2017-11-13 | AMDGPU: Fix not converting d16 load/stores to offset | Matt Arsenault |
| 2017-11-13 | AMDGPU: Implement computeKnownBitsForTargetNode for mbcnt | Matt Arsenault |
| 2017-11-13 | AMDGPU: Fix multi-use shl/add combine | Matt Arsenault |
| 2017-11-13 | AMDGPU: Select d16 loads into low component of register | Matt Arsenault |
| 2017-11-12 | AMDGPU: Fix -enable-var-scope violations | Matt Arsenault |
| 2017-11-12 | AMDGPU: Fix missing gfx9 atomic inc/dec tests | Matt Arsenault |
| 2017-11-10 | [AMDGPU] Prevent Machine Copy Propagation from replacing live copy with the d... | Alexander Timofeev |
| 2017-11-10 | [AMDGPU] Fix pointer info for lowering load/store for r600 for amdgiz environ... | Yaxun Liu |
| 2017-11-10 | [AMDGPU] Fix pointer info for pseudo source for r600 | Yaxun Liu |
| 2017-11-09 | AMDGPU: Merge BUFFER_STORE_DWORD_OFFEN/OFFSET into x2, x4 | Marek Olsak |
| 2017-11-09 | AMDGPU: Lower buffer store and atomic intrinsics manually | Marek Olsak |
| 2017-11-09 | AMDGPU: Merge BUFFER_LOAD_DWORD_OFFSET into x2, x4 | Marek Olsak |
| 2017-11-09 | AMDGPU: Merge BUFFER_LOAD_DWORD_OFFEN into x2, x4 | Marek Olsak |
| 2017-11-09 | AMDGPU: Merge S_BUFFER_LOAD_DWORD_IMM into x2, x4 | Marek Olsak |
| 2017-11-09 | AMDGPU: Fold immediate offset into BUFFER_LOAD_DWORD lowered from SMEM | Marek Olsak |
| 2017-11-08 | AMDGPU: Set correct sched model on v_mad_u64_u32 | Matt Arsenault |
| 2017-11-06 | [MIRPrinter] Use %subreg.xxx syntax for subregister index operands | Bjorn Pettersson |
| 2017-11-06 | AMDGPU: Select v_mad_u64_u32 and v_mad_i64_i32 | Matt Arsenault |
| 2017-11-06 | [AMDGPU] Change alloca addr space of r600 to 5 for amdgiz environment | Yaxun Liu |
| 2017-11-06 | [AMDGPU] Fix assertion due to assuming pointer in default addr space is 32 bit | Yaxun Liu |
| 2017-11-04 | [AMDGPU] Remove hardcoded address space value from AMDGPULibFunc | Yaxun Liu |
| 2017-10-31 | AMDGPU: Select s_buffer_load_dword with a non-constant SGPR offset | Marek Olsak |
| 2017-10-30 | [AMDGPU] Emit metadata for hidden arguments for kernel enqueue | Yaxun Liu |
| 2017-10-27 | AMDGPU/GlobalISel: Mark 32-bit G_FADD as legal | Tom Stellard |
| 2017-10-27 | DAG: Fold fma (fneg x), K, y -> fma x, -K, y | Matt Arsenault |
| 2017-10-26 | AMDGPU: Commit missing fence-barrier test | Konstantin Zhuravlyov |
| 2017-10-26 | AMDGPU: Handle s_buffer_load_dword hazard on SI | Marek Olsak |
