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2017-11-22[AMDGPU] Fix SITargetLowering::LowerCall for pointer info of byval argumentYaxun Liu
SITargetLowering::LowerCall uses dummy pointer info for byval argument, which causes flat load instead of buffer load. This patch fixes that. Differential Revision: https://reviews.llvm.org/D40040 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318844 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-22AMDGPU: Consider memory dependencies with moved instructions in ↵Nicolai Haehnle
SILoadStoreOptimizer Summary: This bug seems to have gone unnoticed because critical cases with LDS instructions are eliminated by the peephole optimizer. However, equivalent situations arise with buffer loads and stores as well, so this fixes regressions since r317751 ("AMDGPU: Merge S_BUFFER_LOAD_DWORD_IMM into x2, x4"). Fixes at least: KHR-GL45.shader_storage_buffer_object.basic-operations-case1-cs KHR-GL45.cull_distance.functional piglit tes-input-gl_ClipDistance.shader_test ... and probably more Change-Id: I0e371536288eb8e6afeaa241a185266fd45d129d Reviewers: arsenm, mareko, rampitec Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D40303 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318829 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-21[AMDGPU] Fix DAGTypeLegalizer::SplitInteger for shift amount typeYaxun Liu
DAGTypeLegalizer::SplitInteger uses default pointer size as shift amount constant type, which causes less performant ISA in amdgcn---amdgiz target since the default pointer type is i64 whereas the desired shift amount type is i32. This patch fixes that by using TLI.getScalarShiftAmountTy in DAGTypeLegalizer::SplitInteger. The X86 change is necessary since splitting i512 requires shifting amount of 256, which cannot be held by i8. Differential Revision: https://reviews.llvm.org/D40148 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318727 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-20[AMDGPU][MC][GFX8][GFX9] Corrected names of integer ↵Dmitry Preobrazhensky
v_{add/addc/sub/subrev/subb/subbrev} See bug 34765: https://bugs.llvm.org//show_bug.cgi?id=34765 Reviewers: tamazov, SamWot, arsenm, vpykhtin Differential Revision: https://reviews.llvm.org/D40088 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318675 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-20[AMDGPU] Update test r600.amdgpu-alias-analysis.llYaxun Liu
Manually update test r600.amdgpu-alias-analysis.ll for amdgiz environment since it cannot be done by script. The two pointers are swapped in the output because PrintResults in AliasAnalysisEvaluator.cpp sorts the strings obtained from printAsOperand before printing them. Differential Revision: https://reviews.llvm.org/D40131 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318660 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-20AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG ↵Valery Pykhtin
(experimental) Differential revision: https://reviews.llvm.org/D39897 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318649 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-17AMDGPU: Move hazard avoidance out of waitcnt pass.Matt Arsenault
This is mostly moving VMEM clause breaking into the hazard recognizer. Also move another hazard currently handled in the waitcnt pass. Also stops breaking clauses unless xnack is enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318557 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-17[AMDGPU][MC][GFX9][disassembler] Corrected decoding of op_sel_hi for v_mad_mix*Dmitry Preobrazhensky
See bug 35148: https://bugs.llvm.org//show_bug.cgi?id=35148 Reviewers: tamazov, SamWot, arsenm Differential Revision: https://reviews.llvm.org/D39492 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318526 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-17AMDGPU: Fix breaking SMEM clausesMatt Arsenault
This was completely ignoring subregisters, so was not very useful. Also only break them if xnack is actually enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318505 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-16Let llvm.invariant.group.barrier accepts pointer to any address spaceYaxun Liu
llvm.invariant.group.barrier may accept pointers to arbitrary address space. This patch let it accept pointers to i8 in any address space and returns pointer to i8 in the same address space. Differential Revision: https://reviews.llvm.org/D39973 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318413 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-16Fix pointer EVT in SelectionDAGBuilder::visitAllocaYaxun Liu
SelectionDAGBuilder::visitAlloca assumes alloca address space is 0, which is incorrect for triple amdgcn---amdgiz and causes isel failure. This patch fixes that. Differential Revision: https://reviews.llvm.org/D40095 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318392 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-16Fix APInt bit size in processDbgDeclaresYaxun Liu
processDbgDeclares assumes pointer size is the same for different addr spaces. It uses pointer size for addr space 0 for all pointers, which causes assertion in stripAndAccumulateInBoundsConstantOffsets for amdgcn---amdgiz since pointer in addr space 5 has different size than in addr space 0. This patch fixes that. Differential Revision: https://reviews.llvm.org/D40085 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318370 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-15AMDGPU: Replace i64 add/sub loweringMatt Arsenault
Use VOP3 add/addc like usual. This has some tradeoffs. Inline immediates fold a little better, but other constants are worse off. SIShrinkInstructions could be made smarter to handle these cases. This allows us to avoid selecting scalar adds where we need to track the carry in scc and replace its users. This makes it easier to use the carryless VALU adds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318340 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-15AMDGPU: Don't use MUBUF vaddr if address may overflowMatt Arsenault
Effectively revert r263964. Before we would not allow this if vaddr was not known to be positive. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318240 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-14AMDGPU: Handle or in multi-use shl ptr combineMatt Arsenault
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318223 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-14[AMDGPU] updated PAL metadata record keysTim Renouf
Summary: The ABI changed before specification was finalized. Reviewers: kzhuravl, dstuttard Subscribers: wdng, nhaehnle, yaxunl, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D39807 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318213 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-14[GISel]: Rework legalization algorithm for better elimination ofAditya Nandakumar
artifacts along with DCE Legalization Artifacts are all those insts that are there to make the type system happy. Currently, the target needs to say all combinations of extends and truncs are legal and there's no way of verifying that post legalization, we only have *truly* legal instructions. This patch changes roughly the legalization algorithm to process all illegal insts at one go, and then process all truncs/extends that were added to satisfy the type constraints separately trying to combine trivial cases until they converge. This has the added benefit that, the target legalizerinfo can only say which truncs and extends are okay and the artifact combiner would combine away other exts and truncs. Updated legalization algorithm to roughly the following pseudo code. WorkList Insts, Artifacts; collect_all_insts_and_artifacts(Insts, Artifacts); do { for (Inst in Insts) legalizeInstrStep(Inst, Insts, Artifacts); for (Artifact in Artifacts) tryCombineArtifact(Artifact, Insts, Artifacts); } while(!Insts.empty()); Also, wrote a simple wrapper equivalent to SetVector, except for erasing, it avoids moving all elements over by one and instead just nulls them out. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318210 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-14AMDGPU: Error on stack size overflowMatt Arsenault
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318189 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-14CodeGen: Fix TargetLowering::LowerCallTo for sret value typeYaxun Liu
TargetLowering::LowerCallTo assumes that sret value type corresponds to a pointer in default address space, which is incorrect, since sret value type should correspond to a pointer in alloca address space, which may not be the default address space. This causes assertion for amdgcn target in amdgiz environment. This patch fixes that. Differential Revision: https://reviews.llvm.org/D39996 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318167 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-14AMDGPU: Fix testMatt Arsenault
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318138 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-14AMDGPU: Fix producing saveexec when the copy is spilledMatt Arsenault
If the register from the copy from exec was spilled, the copy before the spill was deleted leaving a spill of undefined register verifier error and miscompiling. Check for other use instructions of the copy register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318132 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-13AMDGPU: Fix not converting d16 load/stores to offsetMatt Arsenault
Fixes missed optimization with new MUBUF instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318106 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-13AMDGPU: Implement computeKnownBitsForTargetNode for mbcntMatt Arsenault
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318100 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-13AMDGPU: Fix multi-use shl/add combineMatt Arsenault
This was using a custom function that didn't handle the addressing modes properly for private. Use isLegalAddressingMode to avoid duplicating this. Additionally, skip the combine if there is only one use since the standard combine will handle it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318013 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-13AMDGPU: Select d16 loads into low component of registerMatt Arsenault
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318005 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-12AMDGPU: Fix -enable-var-scope violationsMatt Arsenault
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318004 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-12AMDGPU: Fix missing gfx9 atomic inc/dec testsMatt Arsenault
The global instructions weren't tested. Plus there were also some -enable-var-scope violations and broken check prefixes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318003 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10[AMDGPU] Prevent Machine Copy Propagation from replacing live copy with the ↵Alexander Timofeev
dead one Differential revision: https://reviews.llvm.org/D38754 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317884 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10[AMDGPU] Fix pointer info for lowering load/store for r600 for amdgiz ↵Yaxun Liu
environment r600 uses dummy pointer info for lowering load/store. Since dummy pointer info assumes address space 0, this causes isel failure when temporary load/store SDNodes are generated for amdgiz environment. Since the offest is not constant, FixedStack pseudo source value cannot be used to create the pointer info. This patch creates pointer info using llvm undef value. At least this provides correct address space so that isel can be done correctly. Differential Revision: https://reviews.llvm.org/D39698 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317862 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10[AMDGPU] Fix pointer info for pseudo source for r600Yaxun Liu
The pointer info for pseudo source for r600 is not correct when alloca addr space is not 0, which causes invalid SDNode for r600---amdgiz. This patch fixes that. Differential Revision: https://reviews.llvm.org/D39670 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317861 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09AMDGPU: Merge BUFFER_STORE_DWORD_OFFEN/OFFSET into x2, x4Marek Olsak
Summary: Only 56 shaders (out of 48486) are affected. Totals from affected shaders (changed stats only): SGPRS: 2420 -> 2460 (1.65 %) Spilled VGPRs: 94 -> 112 (19.15 %) Scratch size: 524 -> 528 (0.76 %) dwords per thread Code Size: 187400 -> 184992 (-1.28 %) bytes One DiRT Showdown shader spills 6 more VGPRs. One Grid Autosport shader spills 12 more VGPRs. The other 54 shaders only have a decrease in code size. (I'm ignoring the SGPR noise) Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D39012 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317755 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09AMDGPU: Lower buffer store and atomic intrinsics manuallyMarek Olsak
Summary: Without this, SIMemoryLegalizer inserts s_waitcnt vmcnt(0) before every buffer store and atomic instruction. Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D39060 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317754 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09AMDGPU: Merge BUFFER_LOAD_DWORD_OFFSET into x2, x4Marek Olsak
Summary: Only 3 (out of 48486) shaders are affected. Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D38951 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317753 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09AMDGPU: Merge BUFFER_LOAD_DWORD_OFFEN into x2, x4Marek Olsak
Summary: -9.9% code size decrease in affected shaders. Totals (changed stats only): SGPRS: 2151462 -> 2170646 (0.89 %) VGPRS: 1634612 -> 1640288 (0.35 %) Spilled SGPRs: 8942 -> 8940 (-0.02 %) Code Size: 52940672 -> 51727288 (-2.29 %) bytes Max Waves: 373066 -> 371718 (-0.36 %) Totals from affected shaders: SGPRS: 283520 -> 302704 (6.77 %) VGPRS: 227632 -> 233308 (2.49 %) Spilled SGPRs: 3966 -> 3964 (-0.05 %) Code Size: 12203080 -> 10989696 (-9.94 %) bytes Max Waves: 44070 -> 42722 (-3.06 %) Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D38950 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317752 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09AMDGPU: Merge S_BUFFER_LOAD_DWORD_IMM into x2, x4Marek Olsak
Summary: Only constant offsets (*_IMM opcodes) are merged. It reuses code for LDS load/store merging. It relies on the scheduler to group loads. The results are mixed, I think they are mostly positive. Most shaders are affected, so here are total stats only: SGPRS: 2072198 -> 2151462 (3.83 %) VGPRS: 1628024 -> 1634612 (0.40 %) Spilled SGPRs: 7883 -> 8942 (13.43 %) Spilled VGPRs: 97 -> 101 (4.12 %) Scratch size: 1488 -> 1492 (0.27 %) dwords per thread Code Size: 60222620 -> 52940672 (-12.09 %) bytes Max Waves: 374337 -> 373066 (-0.34 %) There is 13.4% increase in SGPR spilling, DiRT Showdown spills a few more VGPRs (now 37), but 12% decrease in code size. These are the new stats for SGPR spilling. We already spill a lot SGPRs, so it's uncertain whether more spilling will make any difference since SGPRs are always spilled to VGPRs: SGPR SPILLING APPS Shaders SpillSGPR AvgPerSh alien_isolation 2938 100 0.0 batman_arkham_origins 589 6 0.0 bioshock-infinite 1769 4 0.0 borderlands2 3968 22 0.0 counter_strike_glob.. 1142 60 0.1 deus_ex_mankind_div.. 1410 79 0.1 dirt-showdown 533 4 0.0 dirt_rally 364 1163 3.2 divinity 1052 2 0.0 dota2 1747 7 0.0 f1-2015 776 1515 2.0 grid_autosport 1767 1505 0.9 hitman 1413 273 0.2 left_4_dead_2 1762 4 0.0 life_is_strange 1296 26 0.0 mad_max 358 96 0.3 metro_2033_redux 2670 60 0.0 payday2 1362 22 0.0 portal 474 3 0.0 saints_row_iv 1704 8 0.0 serious_sam_3_bfe 392 1348 3.4 shadow_of_mordor 1418 12 0.0 shadow_warrior 3956 239 0.1 talos_principle 324 1735 5.4 thea 172 17 0.1 tomb_raider 1449 215 0.1 total_war_warhammer 242 56 0.2 ue4_effects_cave 295 55 0.2 ue4_elemental 572 12 0.0 unigine_tropics 210 56 0.3 unigine_valley 278 152 0.5 victor_vran 1262 84 0.1 yofrankie 82 2 0.0 Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D38949 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317751 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-09AMDGPU: Fold immediate offset into BUFFER_LOAD_DWORD lowered from SMEMMarek Olsak
Summary: -5.3% code size in affected shaders. Changed stats only: 48486 shaders in 30489 tests Totals: SGPRS: 2086406 -> 2072430 (-0.67 %) VGPRS: 1626872 -> 1627960 (0.07 %) Spilled SGPRs: 7865 -> 7912 (0.60 %) Code Size: 60978060 -> 60188764 (-1.29 %) bytes Max Waves: 374530 -> 374342 (-0.05 %) Totals from affected shaders: SGPRS: 299664 -> 285688 (-4.66 %) VGPRS: 233844 -> 234932 (0.47 %) Spilled SGPRs: 3959 -> 4006 (1.19 %) Code Size: 14905272 -> 14115976 (-5.30 %) bytes Max Waves: 46202 -> 46014 (-0.41 %) Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D38915 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317750 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-08AMDGPU: Set correct sched model on v_mad_u64_u32Matt Arsenault
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317645 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-06[MIRPrinter] Use %subreg.xxx syntax for subregister index operandsBjorn Pettersson
Summary: Print %subreg.<subregidxname> instead of just the subregister index when printing immediate operands corresponding to subreg indices in INSERT_SUBREG, EXTRACT_SUBREG, SUBREG_TO_REG and REG_SEQUENCE. Reviewers: qcolombet, MatzeB Reviewed By: MatzeB Subscribers: nhaehnle, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D39696 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317513 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-06AMDGPU: Select v_mad_u64_u32 and v_mad_i64_i32Matt Arsenault
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317492 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-06[AMDGPU] Change alloca addr space of r600 to 5 for amdgiz environmentYaxun Liu
Differential Revision: https://reviews.llvm.org/D39657 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317479 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-06[AMDGPU] Fix assertion due to assuming pointer in default addr space is 32 bitYaxun Liu
The backend assumes pointer in default addr space is 32 bit, which is not true for the new addr space mapping and causes assertion for unresolved functions. This patch fixes that. Differential Revision: https://reviews.llvm.org/D39643 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317476 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-04[AMDGPU] Remove hardcoded address space value from AMDGPULibFuncYaxun Liu
AMDGPULibFunc hardcodes address space values of the old address space mapping, which causes invalid addrspacecast instructions and undefined functions in APPSDK sample MonteCarloAsianDP. This patch fixes that. Differential Revision: https://reviews.llvm.org/D39616 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317409 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-31AMDGPU: Select s_buffer_load_dword with a non-constant SGPR offsetMarek Olsak
Summary: Apps that benefit: - alien isolation - bioshock infinite - civilization: beyond earth - company of heroes 2 - dirt showdown - dota 2 - F1 2015 - grid autosport - hitman - legend of grimrock - serious sam 3: bfe - shadow warrior - talos principle - total war: warhammer - UE4 demos: effects cave, elemental, sun temple Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D38914 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317038 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-30[AMDGPU] Emit metadata for hidden arguments for kernel enqueueYaxun Liu
Identifies kernels which performs device side kernel enqueues and emit metadata for the associated hidden kernel arguments. Such kernels are marked with calls-enqueue-kernel function attribute by AMDGPUOpenCLEnqueueKernelLowering pass and later on hidden kernel arguments metadata HiddenDefaultQueue and HiddenCompletionAction are emitted for them. Differential Revision: https://reviews.llvm.org/D39255 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316907 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-27AMDGPU/GlobalISel: Mark 32-bit G_FADD as legalTom Stellard
Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D38439 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316815 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-27DAG: Fold fma (fneg x), K, y -> fma x, -K, yMatt Arsenault
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316753 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-26AMDGPU: Commit missing fence-barrier testKonstantin Zhuravlyov
This should have been committed with memory model implementation git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316680 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-26AMDGPU: Handle s_buffer_load_dword hazard on SIMarek Olsak
Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D39171 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316666 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-25Fix CodeGen/AMDGPU/fcanonicalize-elimination.ll on FreeBSD 11.0Alexander Richardson
Summary: On FreeBSD11.0 the FileCheck NOT string "1.0" will be matched by `.amd_amdgpu_isa "amdgcn-unknown-freebsd11.0--gfx802"` at the end of the file. Add a CHECK for that directive to avoid failing the test. Reviewers: rampitec, kzhuravl Reviewed By: rampitec, kzhuravl Subscribers: emaste, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits, krytarowski Differential Revision: https://reviews.llvm.org/D39306 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316616 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-25AMDGPU: Cleanup memory legalizer load/store testsKonstantin Zhuravlyov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316590 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-19 11:07:54 +0000