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path: root/test/CodeGen/AMDGPU
AgeCommit message (Expand)Author
2018-04-09Merging r326535:Tom Stellard
2018-02-19Merging r324353:Hans Wennborg
2018-02-02Merging r323908:Hans Wennborg
2018-02-02Merging r323909:Hans Wennborg
2018-01-30Merging r323706:Hans Wennborg
2018-01-30Merging r323355:Hans Wennborg
2018-01-17Merging r321751, r321806, and r321878:Hans Wennborg
2017-12-312nd attempt at "fixing" amdgpu tests after r321575​Philip Reames
2017-12-30Test fix after r321575Philip Reames
2017-12-29AMDGPU: Remove mayLoad/hasSideEffects from MIMG storesMatt Arsenault
2017-12-19[AMDGPU] Turn off MergeConsecutiveStores() before Instruction Selection for A...Mark Searles
2017-12-18[Memcpy Loop Lowering] Remove the fixed int8 lowering.Sean Fertile
2017-12-15Recommit CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.valueYaxun Liu
2017-12-14Revert CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.valueYaxun Liu
2017-12-13CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.valueYaxun Liu
2017-12-12[MachineOperand][MIR] Add isRenamable to MachineOperand.Geoff Berry
2017-12-11LSR: Check more intrinsic pointer operandsMatt Arsenault
2017-12-08AMDGPU/GCN: Bring processors in sync with AMDGPUUsageKonstantin Zhuravlyov
2017-12-08AMDGPU: image_getlod and image_getresinfo do not read memoryMatt Arsenault
2017-12-08AMDGPU: Report Arg's Value name in metadata if kernel_arg_name metadata is no...Konstantin Zhuravlyov
2017-12-07[AMDGPU] Revert "[AMDGPU] Add options for waitcnt pass debugging; add instr c...Mark Searles
2017-12-07[AMDGPU] Add options for waitcnt pass debugging; add instr count in debug out...Mark Searles
2017-12-07[AMDGPU] Add GCNHazardRecognizer::checkInlineAsmHazards() and GCNHazardRecogn...Mark Searles
2017-12-07[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih
2017-12-06AMDGPU Tests: Change a case to be run with -O0Zvi Rackover
2017-12-05AMDGPU: Fix SDWA crash on inline asmMatt Arsenault
2017-12-05AMDGPU: Fix infinite loop with dbg_valueMatt Arsenault
2017-12-05AMDGPU: Fix crash when scheduling DBG_VALUEMatt Arsenault
2017-12-04AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instructionJan Vesely
2017-12-04AMDGPU: Disable fp64 support on pre GCN asicsJan Vesely
2017-12-04AMDGPU: Fix creating invalid copy when adjusting dmaskMatt Arsenault
2017-12-04[CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih
2017-12-04[AMDGPU] SDWA: add support for PRESERVE into SDWA peephole.Sam Kolton
2017-12-03CodeGen: Fix SelectionDAGISel::LowerArguments for sret addr spaceYaxun Liu
2017-12-02CodeGen: Fix pointer info in SplitVecOp_EXTRACT_VECTOR_ELT/SplitVecRes_INSERT...Yaxun Liu
2017-12-01[AMDGPU] SiFixSGPRCopies should not modify non-divergent PHIAlexander Timofeev
2017-11-30AMDGPU: Use carry-less adds in FI eliminationMatt Arsenault
2017-11-30AMDGPU: Use gfx9 carry-less add/sub instructionsMatt Arsenault
2017-11-30[CodeGen] Always use `printReg` to print registers in both MIR and debugFrancis Visoiu Mistrih
2017-11-30[CodeGen] Print "%vreg0" as "%0" in both MIR and debug outputFrancis Visoiu Mistrih
2017-11-30AMDGPU: Allow negative MUBUF vaddr for gfx9Matt Arsenault
2017-11-29AMDGPU: Use stricter regexes for add instructionsMatt Arsenault
2017-11-29AMDGPU: Select DS insts without m0 initializationMatt Arsenault
2017-11-28AMDGPU: Enable IPRAMatt Arsenault
2017-11-28AMDGPU: Add num spilled s/vgprs to metadataKonstantin Zhuravlyov
2017-11-28[CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih
2017-11-28DAG: Legalize truncstores to illegal int typesMatt Arsenault
2017-11-27[AMDGPU] Update test nullptr.ll to use amdgiz environmentYaxun Liu
2017-11-27[DAG] Do MergeConsecutiveStores again before Instruction SelectionNirav Dave
2017-11-27[AMDGPU] Add custom lowering for llvm.log{,10}.{f16,f32} intrinsicsVedran Miletic
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