| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-04-27 | [AArch64] Also combine vector selects fed by non-i1 SETCCs. | Ahmed Bougacha |
| 2015-04-27 | [AArch64] Don't assert when combining (v3f32 select (setcc f64)). | Ahmed Bougacha |
| 2014-12-01 | [AArch64] Don't combine "select (setcc i1 LHS, RHS), vL, vR". | Ahmed Bougacha |
| 2014-07-03 | [codegen,aarch64] Add a target hook to the code generator to control | Chandler Carruth |
| 2014-05-24 | AArch64/ARM64: move ARM64 into AArch64's place | Tim Northover |
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index : ampere-computing/llvm.git | |
| LLVM including Ampere Computing toolchain specific patches |
| summaryrefslogtreecommitdiff |