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path: root/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
AgeCommit message (Expand)Author
2017-12-04[CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih
2017-11-20[AArch64][TableGen] Skip tied result operands for InstAliasSander de Smalen
2017-04-13[AArch64] Avoid partial register writes on lane 0 of BUILD_VECTOR for i8/i16/f16Adam Nemet
2017-04-04[AArch64] Avoid partial register deps on insertelt of load into lane 0.Ahmed Bougacha
2017-02-08Revert r294437 as it broke an asan buildbot.Amara Emerson
2017-02-08[AArch64][TableGen] Skip tied result operands for InstAliasAmara Emerson
2016-11-16[AArch64] Handle vector types in replaceZeroVectorStore.Geoff Berry
2015-12-21[AArch64] Enable PostRAScheduler for AArch64 generic build.Chad Rosier
2015-08-31AArch64: Fix loads to lower NEON vector lanes using GPR registersMatthias Braun
2015-04-17[AArch64] Don't force MVT::Untyped when selecting LD1LANEpost.Ahmed Bougacha
2015-04-17Fix another typo in r235224 testcase. NFC.Ahmed Bougacha
2015-04-17Fix typo in r235224 testcase. NFC.Ahmed Bougacha
2015-04-17[AArch64] Avoid vector->load dependency cycles when creating LD1*post.Ahmed Bougacha
2015-02-27[opaque pointer type] Add textual IR support for explicit type parameter to l...David Blaikie
2015-02-27[opaque pointer type] Add textual IR support for explicit type parameter to g...David Blaikie
2014-05-24AArch64/ARM64: move ARM64 into AArch64's placeTim Northover
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