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AgeCommit message (Expand)Author
2017-12-15Recommit "[DWARFv5] Dump an MD5 checksum in the line-table header."Paul Robinson
2017-12-15Fix unused variable in non-assert buildsMatthias Braun
2017-12-15MachineFunction: Return reference from getFunction(); NFCMatthias Braun
2017-12-15MachineFunction: Slight refactoring; NFCMatthias Braun
2017-12-15Fixed the gcc 'enumeral and non-enumeral type in conditional expression [-Wer...Galina Kistanova
2017-12-15[Hexagon] Remove recursion in visitUsesOf, replace with use queueKrzysztof Parzyszek
2017-12-15[Hexagon] Handle concat_vectors of all allowed HVX typesKrzysztof Parzyszek
2017-12-15[X86] Use AND32ri8 instead of AND64ri8 in Asan code in EmitCallAsanReport for...Craig Topper
2017-12-15[X86] In LowerVectorCTPOP use ISD::ZERO_EXTEND/ISD::TRUNCATE instead of the t...Craig Topper
2017-12-15[X86] Remove unnecessary TODO.Craig Topper
2017-12-15Re-commit : [LICM] Allow sinking when foldable in loopJun Bum Lim
2017-12-15Revert "[DWARFv5] Dump an MD5 checksum in the line-table header."Paul Robinson
2017-12-15[Hexagon] Fix operand-swapping PatFrag for atomic storesKrzysztof Parzyszek
2017-12-15[DWARFv5] Dump an MD5 checksum in the line-table header.Paul Robinson
2017-12-15[X86] Remove assert in X86MCCodeEmitter.cpp that was added in r320830.Craig Topper
2017-12-15[SelectionDAG][X86] Fix insert_vector_elt lowering for v32i1/v64i1 with non-c...Craig Topper
2017-12-15[Memcpy Loop Lowering] Insert loop BB inbetween the split BB.Sean Fertile
2017-12-15[X86] Add 'Requires<[In64BitMode]>' to a bunch of instructions that only have...Craig Topper
2017-12-15[X86] Change BNDLDX to use anymem instead of i64mem for itsmemory operand.Craig Topper
2017-12-15[X86] Remove the 'Requires' In64BitMode/Not64BitMode from the LWP instructions.Craig Topper
2017-12-15[X86] Remove the 'Requires<[In64BitMode]>' from SHSTK instructions.Craig Topper
2017-12-15[TargetLibraryInfo] fix documentation comment; NFCSanjay Patel
2017-12-15[CodeGen] fix documentation comments; NFCSanjay Patel
2017-12-15[AArch64] Fix typo in the ASIMD instruction optimization passEvandro Menezes
2017-12-15fix typo in comment and remove inaccurate comment; NFCSanjay Patel
2017-12-15Fix for bug PR35549 - Repeated schedule comments.Andrew V. Tischenko
2017-12-15Revert "Re-commit : [LICM] Allow sinking when foldable in loop"Jun Bum Lim
2017-12-15Re-commit : [LICM] Allow sinking when foldable in loopJun Bum Lim
2017-12-15Updated llvm-objdump to display local relocations in Mach-O binariesMichael Trent
2017-12-15[X86] Fix XSAVE64 and similar instructions to not be allowed by the assembler...Craig Topper
2017-12-15Revert "[LICM] Allow sinking when foldable in loop"Jun Bum Lim
2017-12-15[CodeGen] Print stack object references as %(fixed-)stack.0 in both MIR and d...Francis Visoiu Mistrih
2017-12-15[ThinLTO] Disallow multiple prevailing defsEugene Leviant
2017-12-15[X86] Widen (v2i32 (fp_to_uint v2f64)) to (v8i32 (fp_to_uint v8f64)) during l...Craig Topper
2017-12-15[LICM] Allow sinking when foldable in loopJun Bum Lim
2017-12-15[MIR] Add support for missing CFI directivesFrancis Visoiu Mistrih
2017-12-15[InlineCost] Find repeated loads in the calleeHaicheng Wu
2017-12-15Fix the second build bot break introduced by r320791.Nemanja Ivanovic
2017-12-15Fix code causing fallthrough warnings in the PPC back end.Nemanja Ivanovic
2017-12-15[RISCV] Change shift amount operand of RVC shift instructions to uimmlog2xlen...Alex Bradbury
2017-12-15Fix the build bot break introduced by r320791.Nemanja Ivanovic
2017-12-15[RISCV] Enable emission of alias instructions by defaultAlex Bradbury
2017-12-15[PM] port Rewrite Statepoints For GC to the new pass manager.Fedor Sergeev
2017-12-15[LLVMgold] Don't set undefined symbol as prevailingEugene Leviant
2017-12-15[PowerPC] Convert r+r instructions to r+i (pre and post RA)Nemanja Ivanovic
2017-12-15[X86] Fix a couple bugs in my recent changes to vXi1 insert_subvector lowering.Craig Topper
2017-12-15[SCEV] Fix the movement of insertion point in expander. PR35406.Serguei Katkov
2017-12-15Recommit CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.valueYaxun Liu
2017-12-15Disabling r312514 as it causes miscompiles that show up on bootstrapNemanja Ivanovic
2017-12-15[X86] Add a TODO about v8i1 CONCAT_VECTORS.Craig Topper
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