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AgeCommit message (Expand)Author
2017-12-11LSR: Check more intrinsic pointer operandsMatt Arsenault
2017-12-11Revert r320407 "[InstCombine] Fix PR35618: Instcombine hangs on single minmax...Hans Wennborg
2017-12-11[CodeGen] Improve the consistency of instruction fusion*Evandro Menezes
2017-12-11ASAN: Provide reliable debug info for local variables at -O0.Adrian Prantl
2017-12-11[PowerPC] Partially enable the ISEL expansion pass.Tony Jiang
2017-12-11[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.Alexey Bataev
2017-12-11[Hexagon] Add support for Hexagon V65Krzysztof Parzyszek
2017-12-11[dwarfdump] Fix off-by-one bug in accelerator table extractor.Jonas Devlieghere
2017-12-11Normalize line endings. NFCI.Simon Pilgrim
2017-12-11[GlobalISel] Disable GISel for big endian.Amara Emerson
2017-12-11[X86] Add LWP schedule testsSimon Pilgrim
2017-12-11[MSan] Hotfix compilationAlexander Potapenko
2017-12-11[AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tmaDmitry Preobrazhensky
2017-12-11[DAGCombiner] protect against an infinite loop between shl <--> mul (PR35579)Sanjay Patel
2017-12-11[MSan] introduce getShadowOriginPtr(). NFC.Alexander Potapenko
2017-12-11[Hexagon] Crash in instruction selection for insert_vector_elt for HVXKrzysztof Parzyszek
2017-12-11[PowerPC] Sign-extend negative constant storesNemanja Ivanovic
2017-12-11[DAGCombiner] Add combined indexed load to the work listNemanja Ivanovic
2017-12-11[RISCV] Add custom CC_RISCV calling convention and improved call supportAlex Bradbury
2017-12-11[RISCV] Allow lowering of dynamic_stackalloc, stacksave, stackrestoreAlex Bradbury
2017-12-11[RISCV] Implement prolog and epilog insertionAlex Bradbury
2017-12-11[ARM] Use ADDCARRY / SUBCARRYRoger Ferrer Ibanez
2017-12-11[RISCV] Support lowering FrameIndexAlex Bradbury
2017-12-11[mips] Removal of microMIPS64R6Aleksandar Beserminji
2017-12-11[AVR] Implement some missing code pathsDylan McKay
2017-12-11[AVR] Fix incorrectly-calculated AVRMCExpr evaluationsDylan McKay
2017-12-11[DAGCombiner] Support folding (mulhs/u X, 0)->0 for vectors.Craig Topper
2017-12-11[DAGCombiner] Reuse existing SDLoc variable instead of creating a new one. NFCCraig Topper
2017-12-10[X86] Add VCOMISDZrr, VCOMISSZrr, VUCOMISDZrr, and VUCOMISSZrr to the skylake...Craig Topper
2017-12-10[X86] Rename some instructions that start with Int_ to have the _Int at the end.Craig Topper
2017-12-10[X86][X87] Fix typo in znver1 FIST/FISTT schedule patternsSimon Pilgrim
2017-12-10[X86] Rename some instructions from 'rb' to 'rrb' to make 'b' a proper suffix...Craig Topper
2017-12-10[X86] Add VCVTQQ2PS to the skylake server scheduler models.Craig Topper
2017-12-10[X86] Add VPMULLWZ256 to the skylake server scheduler modelCraig Topper
2017-12-10[X86] Add 256/512-bit EVEX VPSADBW instructions to skylake server scheduler m...Craig Topper
2017-12-10[X86] Fix a few instructions that were named Z512 instead of just Z.Craig Topper
2017-12-10[X86] Add VPSRLWZrr to skylake server scheduler model.Craig Topper
2017-12-10[X86] Add VPUNPCKLWDZrr to skylake server scheduler model.Craig Topper
2017-12-10[X86] Adjust tablegen includes so we can use Instructions in scheduler models...Craig Topper
2017-12-10[SimplifyLibCalls] propagate FMF when folding pow(x, -1.0) callSanjay Patel
2017-12-10[SimplifyLibCalls] propagate FMF when folding pow(x, 2.0) call (PR35601)Sanjay Patel
2017-12-10[X86] Flag BroadWell scheduler model as completeSimon Pilgrim
2017-12-10Strip trailing whitespace. NFCI.Simon Pilgrim
2017-12-10[X86] Flag ZNVER1 scheduler model as completeSimon Pilgrim
2017-12-10[X86] Flag SLM scheduler model as completeSimon Pilgrim
2017-12-10[X86][AVX[ Tag VZEROALL/VZEROUPPER instructions scheduler classesSimon Pilgrim
2017-12-10[X86] Tag SSE4A instructions as SSE INTALU scheduler classesSimon Pilgrim
2017-12-10[X86] Flag BTVER2 scheduler model as completeSimon Pilgrim
2017-12-10[X86] Tag ADJSTACK instructions as INTALU scheduler classSimon Pilgrim
2017-12-10[SCEV] Fix wrong Equal predicate created in getAddRecForPhiWithCastsDorit Nuzman
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