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AgeCommit message (Expand)Author
2018-01-24Merging r322900 and r323307:Hans Wennborg
2018-01-24Merging r323190:Hans Wennborg
2018-01-24Merging r322372 and r322767:Hans Wennborg
2018-01-22Merging r323034:Hans Wennborg
2018-01-22Merging r322878:Hans Wennborg
2018-01-19Merging r322053:Hans Wennborg
2018-01-18Merging r322644:Hans Wennborg
2018-01-18Merging r322724:Hans Wennborg
2018-01-17Merging r322003:Hans Wennborg
2018-01-17Merging r321751, r321806, and r321878:Hans Wennborg
2018-01-17Merging r322313:Hans Wennborg
2018-01-17Merging r322223:Hans Wennborg
2018-01-17Merging r322106:Hans Wennborg
2018-01-17Merging r322272:Hans Wennborg
2018-01-17Merging r321870, r321872, and r321994:Hans Wennborg
2018-01-17Merging r322473:Hans Wennborg
2018-01-17Merging r321791 and r321862:Hans Wennborg
2018-01-17Merging r321991:Hans Wennborg
2018-01-17Merging r321993:Hans Wennborg
2018-01-17Merging r322623:Hans Wennborg
2018-01-17Merging r322056:Hans Wennborg
2018-01-16Merging r321789:Hans Wennborg
2018-01-16Merging r322103:Hans Wennborg
2018-01-03Remove left-over debug printout from r321692Hans Wennborg
2018-01-03[InstSimplify] Missed optimization in math expression: squashing exp(log), lo...Dmitry Venikov
2018-01-03[ARM][NFC] Avoid recreating MCSubtargetInfo in ARMAsmBackendAlex Bradbury
2018-01-03[AArch64][SVE] Asm: Add restricted register classes for SVE predicate vectors.Sander de Smalen
2018-01-03Fix build of WebAssembly and AVR backends after r321692Alex Bradbury
2018-01-03Thread MCSubtargetInfo through Target::createMCAsmBackendAlex Bradbury
2018-01-03[GlobalISel][Legalizer] Fix legalization of llvm.smul.with.overflowAmara Emerson
2018-01-02Handle the case of live 16-bit subregisters in X86FixupBWInstsAndrew Kaylor
2018-01-02[ValueTracking] recognize min/max of min/max patternsSanjay Patel
2018-01-02[AArch64][GlobalISel] Fix assert fail with unknown intrinsic.Amara Emerson
2018-01-02[x86] allow pairs of PCMPEQ for vector-sized integer equality comparisons (PR...Sanjay Patel
2018-01-02[AArch64][GlobalISel] Enable GlobalISel at -O0 by defaultAmara Emerson
2018-01-02[BasicBlockUtils] Check for unreachable preds before updating LI in UpdateAna...Anna Thomas
2018-01-02[Hexagon] Fix generation of vector sign extensionsKrzysztof Parzyszek
2018-01-02Revert r321089: "[DAG] Elide overlapping store" (and subsequent fix in r321204)Daniel Jasper
2018-01-02[AArch64][AsmParser] Add isScalarReg() and repurpose isReg()Sander de Smalen
2018-01-02Strip trailing whitespace. NFCISimon Pilgrim
2018-01-02[RISCV] Add Defs Uses information for c.jal and c.addi4spnAlex Bradbury
2018-01-02[RISCV][NFC] Resolve unused variable warning in RISCVISelLoweringAlex Bradbury
2018-01-02[DAGCombine] Fix for PR35765Sam Parker
2018-01-02[SelectionDAG] Teach WidenVecOp_Convert to widen the operation if a widened r...Craig Topper
2018-01-02[InstCombine] Missed optimization in math expression: squashing sqrt functionsDmitry Venikov
2018-01-02Test commitDmitry Venikov
2018-01-02[SelectionDAG] Remove ifs on getTypeAction being TypeWidenVector from some of...Craig Topper
2018-01-01[ValueTracking] Don't assume shift values are in rangeSimon Pilgrim
2018-01-01[X86] Promote vXi1 fp_to_uint/fp_to_sint to vXi32 to avoid scalarization.Craig Topper
2018-01-01[X86] Replace custom lowering of vXi1 SINT_TO_FP/UINT_TO_FP with promotion.Craig Topper
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