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AgeCommit message (Expand)Author
2017-12-19Fix Wasm as a follow up to r321035 and the other oneReid Kleckner
2017-12-19TargetLoweringBase: Followup to r321035Matthias Braun
2017-12-19TargetLowering: Fix InitLibcallCallingConvs() overriding things set in InitLi...Matthias Braun
2017-12-18TargetLoweringBase: Remove unnecessary watchos exception; NFCMatthias Braun
2017-12-18[X86] Don't use NOPL when the assembler is passed an empty CPU string.Craig Topper
2017-12-18LiveStacks: Rename LiveStack.{h|cpp} to LiveStacks.{h|cpp}; NFCMatthias Braun
2017-12-18X86/AArch64/ARM: Factor out common sincos_stret logic; NFCIMatthias Braun
2017-12-18AArch64/X86: Factor out common bzero logic; NFCMatthias Braun
2017-12-18[Hexagon] Cache loads to select to avoid traversing mutating DAGKrzysztof Parzyszek
2017-12-18Revert part of r321026 "[X86] Don't use NOPL when the assembler is passed an ...Craig Topper
2017-12-18Fix buffer overrun in WindowsResourceCOFFWriter::writeSymbolTable()Bob Haarman
2017-12-18[MachineOutliner][NFC] Gardening: use std::any_of instead of bool + loopJessica Paquette
2017-12-18[X86] Don't use NOPL when the assembler is passed an empty CPU string. Update...Craig Topper
2017-12-18Revert "[AArch64][SVE] Asm" changes, they broke libjpeg_turboReid Kleckner
2017-12-18[Analysis] Generate more precise TBAA tags when one access encloses the otherIvan A. Kosarev
2017-12-18[PGO] Fix handling of cold entry count for instrumented PGOTeresa Johnson
2017-12-18Fix more inconsistent line endings. NFC.Dimitry Andric
2017-12-18[X86] Minor formatting fix to getHostCPUFeatures. NFCCraig Topper
2017-12-18[MachineOutliner] Recommit r320229Jessica Paquette
2017-12-18[PPC] Also disable the pre-emit version of reg+reg to reg+imm transformation.Benjamin Kramer
2017-12-18Recommit "[DWARFv5] Dump an MD5 checksum in the line-table header."Paul Robinson
2017-12-18[PPC] Disable reg+reg to reg+imm transformation.Benjamin Kramer
2017-12-18Fix inconsistent line endings in HexagonVectorLoopCarriedReuse.cpp. NFC.Dimitry Andric
2017-12-18[Hexagon] Higher versions of HVX imply presence of lower versionsKrzysztof Parzyszek
2017-12-18[IR] Support the new TBAA metadata format in IR verifierIvan A. Kosarev
2017-12-18Fix inconsistent line endings in ARCDisassembler.cpp. NFC.Dimitry Andric
2017-12-18i[Hexagon] ANY_EXTEND_VECTOR_INREG should be Custom, not Legal in r321004Krzysztof Parzyszek
2017-12-18[Hexagon] Generate HVX code for vector sign-, zero- and any-extendsKrzysztof Parzyszek
2017-12-18[Hexagon] Prefer to widen HVX vectors instead of promotingKrzysztof Parzyszek
2017-12-18Removed unused DominanceFrontierMatt Arsenault
2017-12-18[PGO] add MST min edge selection heuristic to ensure non-zero entry countXinliang David Li
2017-12-18[YAML] Add support for non-printable charactersFrancis Visoiu Mistrih
2017-12-18[IR] Add MDBuilder helpers for the new TBAA metadata formatIvan A. Kosarev
2017-12-18[AArch64][SVE] Asm: Improve diagnostics further when +sve is not specifiedSander de Smalen
2017-12-18Reland "[mips] Fix the target specific instruction verifier"Simon Dardis
2017-12-18[Memcpy Loop Lowering] Remove the fixed int8 lowering.Sean Fertile
2017-12-18[LVI] Support for ashr in LVIMax Kazantsev
2017-12-18[ARM GlobalISel] Fix G_(UN)MERGE_VALUES handling after r319524Diana Picus
2017-12-18[ConstantRange] Support for ashr in ConstantRange computationMax Kazantsev
2017-12-18Revert "[mips] Fix the target specific instruction verifier"Simon Dardis
2017-12-18[mips] Fix the target specific instruction verifierSimon Dardis
2017-12-18[AArch64][SVE] Asm: Add ZIP1/ZIP2 instructions (predicate/data vectors)Sander de Smalen
2017-12-18[AArch64][SVE] Asm: Add SVE predicate register definitions and parsing supportSander de Smalen
2017-12-18[ThinLTO] Remove unused codeEugene Leviant
2017-12-18AArch64: work around how Cyclone handles "movi.2d vD, #0".Tim Northover
2017-12-18[TargetLibraryInfo] Discard library functions with incorrectly sized integersIgor Laevsky
2017-12-18[DAGCombine] Move AND nodes to multiple load leavesSam Parker
2017-12-18[NFC][CodeGen][ExpandMemCmp] Fix documentation.Clement Courbet
2017-12-18[SROA] Disable non-whole-alloca splits by defaultHiroshi Inoue
2017-12-18[X86] Fix mistake that I made when splitting up the setOperationAction calls ...Craig Topper
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