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2016-11-01[RISCV] Add stub backendAlex Bradbury
This contains just enough for lib/Target/RISCV to compile. Notably a basic RISCVTargetMachine and RISCVTargetInfo. At this point you can attempt llc -march=riscv32 myinput.ll and will find it fails due to the lack of MCAsmInfo. See http://lists.llvm.org/pipermail/llvm-dev/2016-August/103748.html for further discussion Differential Revision: https://reviews.llvm.org/D23560 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285712 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-01AMDGPU: Fix buildbots broken by r285704Tom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285711 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-01[RISCV] Add RISC-V ELF definesAlex Bradbury
Add the necessary definitions for RISC-V ELF files, including relocs. Also make necessary trivial change to ELFYaml, llvm-objdump, and llvm-readobj in order to work with RISC-V ELFs. Differential Revision: https://reviews.llvm.org/D23557 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285708 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-01[RISCV] Recognise riscv32 and riscv64 in triple parsing codeAlex Bradbury
This is the first in a series of 10 initial patches that incrementally add an MC layer for RISC-V to LLVM. See <http://lists.llvm.org/pipermail/llvm-dev/2016-August/103748.html> for more discussion. Differential Revision: https://reviews.llvm.org/D23557 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285707 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-01[TableGen] Move OperandMatchResultTy enum to MCTargetAsmParser.hAlex Bradbury
As it stands, the OperandMatchResultTy is only included in the generated header if there is custom operand parsing. However, almost all backends make use of MatchOperand_Success and friends from OperandMatchResultTy for e.g. parseRegister. This is a pain when starting an AsmParser for a new backend that doesn't yet have custom operand parsing. Move the enum to MCTargetAsmParser.h. This patch is a prerequisite for D23563 Differential Revision: https://reviews.llvm.org/D23496 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285705 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-01AMDGPU: Implement expansion of f16 = FP_TO_FP16 f64Tom Stellard
I wanted to implement this as a target independent expansion, however when targets say they want to expand FP_TO_FP16 what they actually want is the unsafe math expansion when possible and expansion to a libcall in all other cases. The only way to make this work as a target independent would be to add logic to target's TargetLowering construction to mark theses nodes as Expand when LegalizeDAG can use the unsafe expansion and mark them as LibCall when it cannot. I think this would be possible, but I think it would be too fragile and complex as it would require targets to keep their expansion logic up to date with the code in LegalizeDAG. Reviewers: bogner, ab, t.p.northover, arsenm Subscribers: wdng, llvm-commits, nhaehnle Differential Revision: https://reviews.llvm.org/D25999 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285704 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-01[InstCombine] Folding of shifts by the sum of positive valuesSimon Pilgrim
This patch introduces the combine: (C1 shift (A add C2)) -> ((C1 shift C2) shift A) iff A and C2 are both positive If both A and C2 are know to be positive then we can safely split into 2 shifts, permitting the folding of the Inner shift. Fix for the spec benchmark case mentioned by @nadav on PR15141 (assuming we can prove that the inputs as positive). Differential Revision: https://reviews.llvm.org/D26000 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285696 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-01[Thumb-1] Synthesize TBB/TBH instructions to make use of compressed jump tablesJames Molloy
[Reapplying r284580 and r285917 with fix and testing to ensure emitted jump tables for Thumb-1 have 4-byte alignment] The TBB and TBH instructions in Thumb-2 allow jump tables to be compressed into sequences of bytes or shorts respectively. These instructions do not exist in Thumb-1, however it is possible to synthesize them out of a sequence of other instructions. It turns out this sequence is so short that it's almost never a lose for performance and is ALWAYS a significant win for code size. TBB example: Before: lsls r0, r0, #2 After: add r0, pc adr r1, .LJTI0_0 ldrb r0, [r0, #6] ldr r0, [r0, r1] lsls r0, r0, #1 mov pc, r0 add pc, r0 => No change in prologue code size or dynamic instruction count. Jump table shrunk by a factor of 4. The only case that can increase dynamic instruction count is the TBH case: Before: lsls r0, r4, #2 After: lsls r4, r4, #1 adr r1, .LJTI0_0 add r4, pc ldr r0, [r0, r1] ldrh r4, [r4, #6] mov pc, r0 lsls r4, r4, #1 add pc, r4 => 1 more instruction in prologue. Jump table shrunk by a factor of 2. So there is an argument that this should be disabled when optimizing for performance (and a TBH needs to be generated). I'm not so sure about that in practice, because on small cores with Thumb-1 performance is often tied to code size. But I'm willing to turn it off when optimizing for performance if people want (also note that TBHs are fairly rare in practice!) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285690 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-01[AMDGPU] Expand vector mulhu/mulhsValery Pykhtin
Differential revision: https://reviews.llvm.org/D26077 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285684 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-01[PowerPC] Implement vector shift builtins - llvm portionNemanja Ivanovic
This patch corresponds to review https://reviews.llvm.org/D26095. Committing on behalf of Tony Jiang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285681 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-01Allow resolving response file names relative to including fileSerge Pavlov
If a response file included by construct @file itself includes a response file and that file is specified by relative file name, current behavior is to resolve the name relative to the current working directory. The change adds additional flag to ExpandResponseFiles that may be used to resolve nested response file names relative to including file. With the new mode a set of related response files may be kept together and reference each other with short position independent names. Differential Revision: https://reviews.llvm.org/D24917 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285675 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-01[TBAA] Use wrapper objects instead of raw getOperand s; NFCSanjoy Das
This is intended to make the semantic intent clearer. The wrapper objects are now generic to avoid `const_cast` s. Since `const` ness is part of the API of `MDNode::getMostGenericTBAA` (and therefore I can't make things `const` all the way through without some code churn outside TypeBasedAliasAnalysis.cpp), this seemed like the cleanest solution. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285665 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-01[TBAA] Rename accessors to be more idiomatic; NFCSanjoy Das
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285661 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-01Bitcode: Simplify BitstreamWriter::EnterBlockInfoBlock() interface.Peter Collingbourne
No block info block should need to define local abbreviations, so we can always use a code width of 2. Also change all block info block writers to use EnterBlockInfoBlock. Differential Revision: https://reviews.llvm.org/D26168 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285660 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-01AMDGPU: Whitespace fixesMatt Arsenault
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285659 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-31[DAG] disable nsw/nuw for add/sub/mul when simplifying based on demanded ↵Sanjay Patel
bits (PR30841) This bug was exposed by using nsw/nuw for more aggressive folds in: https://reviews.llvm.org/rL284844 The changes mimic the IR demanded bits logic in InstCombiner::SimplifyDemandedUseBits(), but we can't just flip flag bits in the DAG; we have to create a new node that has the bits cleared. This should fix: https://llvm.org/bugs/show_bug.cgi?id=30841 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285656 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-31[Hexagon] Garbage collect dead code.Davide Italiano
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285654 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-31Fix a typo.Evgeniy Stepanov
Found with PVS-Studio here: http://www.viva64.com/en/b/0446/ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285652 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-31CodeGen: further loosen -O0 CG for WoA divisionSaleem Abdulrasool
Generate the slowest possible codepath for noopt CodeGen. Even trying to be clever with the negated jump can cause out-of-range jumps. Use a wide branch instead. Although the code is modelled simplistically, the later optimizations would recombine the branching into `cbz` if possible. This re-enables the previous optimization as well as hopefully gives us working code in all cases. Addresses PR30356! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285649 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-31[ThinLTO] Disable importing and other cross-module optis at -O0Teresa Johnson
Summary: There is no point to importing at -O0, since we won't inline. We should also disable other cross-module optimizations. (Plan to backport this fix to the 3.9 branch to fix PR30774) Reviewers: pcc Subscribers: johanengelen, mehdi_amini Differential Revision: https://reviews.llvm.org/D25918 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285648 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-31[NVPTX] Remove NVPTXFavorNonGenericAddrSpaces pass.Justin Lebar
Summary: This has been replaced by the NVPTXInferAddressSpaces pass. We've had the new one as the default with the old one accessible via a flag for some months now, and we've had no problems. Reviewers: tra Subscribers: llvm-commits, jholewinski, jingyue, mgorny Differential Revision: https://reviews.llvm.org/D26165 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285642 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-31More additional error checks for invalid Mach-O files whenKevin Enderby
the offsets and sizes of an element of the file overlaps with another element in the Mach-O file. This shows the approach to this testing for three elements and contains for tests for their overlap. Checking for all the remain elements will be added next. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285632 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-31[PPC] add absolute difference altivec instructions and matching intrinsicsNemanja Ivanovic
This patch corresponds to review https://reviews.llvm.org/D26072. Committing on behalf of Sean Fertile. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285627 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-31DebugInfo: make DW_TAG_atomic_type validVictor Leschuk
DW_TAG_atomic_type was already included in Dwarf.defs and emitted correctly, however Verifier didn't recognize it as valid. Thus we introduce the following changes: * Make DW_TAG_atomic_type valid tag for IR and DWARF (enabled only with -gdwarf-5) * Add it to related docs * Add DebugInfo tests Differential Revision: https://reviews.llvm.org/D26144 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285624 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-31[asan] Move instrumented null-terminated strings to a special section, LLVM partKuba Brecka
On Darwin, simple C null-terminated constant strings normally end up in the __TEXT,__cstring section of the resulting Mach-O binary. When instrumented with ASan, these strings are transformed in a way that they cannot be in __cstring (the linker unifies the content of this section and strips extra NUL bytes, which would break instrumentation), and are put into a generic __const section. This breaks some of the tools that we have: Some tools need to scan all C null-terminated strings in Mach-O binaries, and scanning all the contents of __const has a large performance penalty. This patch instead introduces a special section, __asan_cstring which will now hold the instrumented null-terminated strings. Differential Revision: https://reviews.llvm.org/D25026 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285619 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-31GlobalISel: allow truncating pointer casts on AArch64.Tim Northover
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285615 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-31GlobalISel: translate stack protector intrinsicsTim Northover
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285614 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-31Define DbiStreamBuilder::addSectionMap.Rui Ueyama
This change enables LLD to construct a Section Map stream in a PDB file. I do not understand all these fields in the Section Map yet, but it seems like a copy of a COFF section header in another format. With this patch, DbiStreamBuilder can emit a Section Map which llvm-pdbdump can dump. Differential Revision: https://reviews.llvm.org/D26112 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285606 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-31Modify DWARFFormValue to remember the DWARFUnit that it was decoded with.Greg Clayton
Modifying DWARFFormValue to remember the DWARFUnit that it was encoded with can simplify the usage of instances of this class. Previously users would have to try and pass in the same DWARFUnit that was used to decode the form value and there was a possibility that a different DWARFUnit might be supplied to the functions that extract values (strings, CU relative references, addresses) and cause problems. This fixes this potential issue by storing the DWARFUnit inside the DWARFFormValue so that this mistake can't be made. Instances of DWARFFormValue are not stored permanently and are used as temporary values, so the increase in size of an instance of DWARFFormValue isn't a big deal. This makes decoding form values more bullet proof and is a change that will be used by future modifications. https://reviews.llvm.org/D26052 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285594 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-31[x86][inline-asm][AVX512][llvm][PART-2]Michael Zuckerman
Introducing "k" and "Yk" constraints for extended inline assembly, enabling use of AVX512 masked vectorized instructions. Commit on behalf of mharoush Extending inline assembly support, compatible with GCC as folowing: "k" constraint hints the compiler to select any of AVX512 k0-k7 registers. "Yk" constraint is a subset of "k" excluding k0 which is not allowd to be used as a mask. Reviewer: 1. rnk Differential Revision: https://reviews.llvm.org/D25062 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285591 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-31[AMDGPU][MC][gfx8] Support 20-bit immediate offset in SMEM instructions.Artem Tamazov
Fixes Bug 30808. Note that passing subtarget information to predicates seems too complicated, so gfx8-specific def smrd_offset_20 introduced. Old gfx6/7-specific def renamed to smrd_offset_8 for clarity. Lit tests updated. Differential Revision: https://reviews.llvm.org/D26085 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285590 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-31[Hexagon] Don't expand mux instructions with both sources identicalKrzysztof Parzyszek
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285588 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-31[SystemZ] Rework processor feature definitions and add -mcpu=archX supportUlrich Weigand
This patch implements two changes: - Move processor feature definition into a new file SystemZFeatures.td, and provide explicit lists of supported and unsupported features for each level of the z/Architecture. This allows specifying unsupported features in the scheduler definition files for each processor. - Add optional aliases for the -mcpu processor names according to the level of the z/Architecture, for compatibility with other compilers on the platform. The supported aliases are: -mcpu=arch8 equals -mcpu=z10 -mcpu=arch9 equals -mcpu=z196 -mcpu=arch10 equals -mcpu=zEC12 -mcpu=arch11 equals -mcpu=z13 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285577 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-31[SystemZ] Guard LEFR/LFER with FeatureVectorUlrich Weigand
The LEFR/LFER pseudos are aliases for vector instructions and should therefore be guared by FeatureVector. If they aren't, the TableGen scheduler definition checking might complain that there is no data for those pseudos for pre-z13 machines. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285576 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-31[SystemZ] Correctly diagnose missing features in AsmParserUlrich Weigand
Currently, when using an instruction that is not supported on the currently selected architecture, the LLVM assembler is likely to diagnose an "invalid operand" instead of a "missing feature". This is because many operands require a custom parser in order to be processed correctly, and if an instruction is not available according to the current feature set, the generated parser code will also not detect the associated custom operand parsers. Fixed by temporarily enabling all features while parsing operands. The missing features will then be correctly detected when actually parsing the instruction itself. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285575 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-31[SystemZ] Fix encoding of MVCK and .insn ssUlrich Weigand
LLVM currently treats the first operand of MVCK as if it were a regular base+index+displacement address. However, it is in fact a base+displacement combined with a length register field. While the two might look syntactically similar, there are two semantic differences: - %r0 is a valid length register, even though it cannot be used as an index register. - In an expression with just a single register like 0(%rX), the register is treated as base with normal addresses, while it is treated as the length register (with an empty base) for MVCK. Fixed by adding a new operand parser class BDRAddr and reworking the assembler parser to distinguish between address + length register operands and regular addresses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285574 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-31Second attempt at r285517.Dorit Nuzman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285568 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-31[SystemZ] Model 2 VBU units (not 1) in SystemZScheduleZ13.td.Jonas Paulsson
NFC. Review: Ulrich Weigand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285566 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-31Improved cost model for FDIV and FSQRT, by Andrew TischenkoAlexey Bataev
There is a bug describing poor cost model for floating point operations: Bug 29083 - [X86][SSE] Improve costs for floating point operations. This patch is the second one in series of patches dealing with cost model. Differential Revision: https://reviews.llvm.org/D25722 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285564 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-31[AVX-512] Add missing patterns for selecting masked vector extracts that ↵Craig Topper
started from shuffles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285546 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-31[SCEV] Try to order n-ary expressions in CompareValueComplexitySanjoy Das
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285535 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-30[SCEV] In CompareValueComplexity, order global values by their nameSanjoy Das
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285529 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-30[SCEV] Use auto for consistency with an upcoming change; NFCSanjoy Das
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285528 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-30[DAG] x | x --> xSanjay Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285522 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-30[DAG] x & x --> xSanjay Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285521 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-30Revert r285517 due to build failures.Dorit Nuzman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285518 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-30[LoopVectorize] Make interleaved-accesses analysis less conservative aboutDorit Nuzman
possible pointer-wrap-around concerns, in some cases. Before this patch, collectConstStridedAccesses (part of interleaved-accesses analysis) called getPtrStride with [Assume=false, ShouldCheckWrap=true] when examining all candidate pointers. This is too conservative. Instead, this patch makes collectConstStridedAccesses use an optimistic approach, calling getPtrStride with [Assume=true, ShouldCheckWrap=false], and then, once the candidate interleave groups have been formed, revisits the pointer-wrapping analysis but only where it matters: namely, in groups that have gaps, and where the gaps are not at the very end of the group (in which case the loop is peeled). This second time getPtrStride is called with [Assume=false, ShouldCheckWrap=true], but this could further be improved to using Assume=true, once we also add the logic to track that we are not going to meet the scev runtime checks threshold. Differential Revision: https://reviews.llvm.org/D25276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285517 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-30[X86] Use intrinsics table for PMADDUBSW and PMADDWD so that we can use the ↵Craig Topper
legacy intrinsics to select EVEX encoded instructions when available. This removes a couple tablegen classes that become unused after this change. Another class gained an additional parameter to allow PMADDUBSW to specify a different result type from its input type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285515 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-30[ThinLTO] Use per-summary flag to prevent exporting locals used in inline asmTeresa Johnson
Summary: Instead of using the workaround of suppressing the entire index for modules that call inline asm that may reference locals, use the NoRename flag on the summary for any locals in the llvm.used set, and add a reference edge from any functions containing inline asm. This avoids issues from having no summaries despite the module defining global values, which was preventing more aggressive index-based optimization. It will be followed by a subsequent patch to make a similar fix for local references in module level asm (to fix PR30610). Reviewers: mehdi_amini Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D26121 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285513 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-30[ThinLTO] Correctly resolve linkonce when importing aliaseeTeresa Johnson
Summary: When we have an aliasee that is linkonce, while we can't convert the non-prevailing copies to available_externally, we still need to convert the prevailing copy to weak. If a reference to the aliasee is exported, not converting a copy to weak will result in undefined references when the linkonce is removed in its original module. Add a new test and update existing tests. Reviewers: mehdi_amini Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D26076 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285512 91177308-0d34-0410-b5e6-96231b3b80d8
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