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AgeCommit message (Expand)Author
2017-12-15[PowerPC] Convert r+r instructions to r+i (pre and post RA)Nemanja Ivanovic
2017-12-15[X86] Fix a couple bugs in my recent changes to vXi1 insert_subvector lowering.Craig Topper
2017-12-15[SCEV] Fix the movement of insertion point in expander. PR35406.Serguei Katkov
2017-12-15Recommit CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.valueYaxun Liu
2017-12-15Disabling r312514 as it causes miscompiles that show up on bootstrapNemanja Ivanovic
2017-12-15[X86] Add a TODO about v8i1 CONCAT_VECTORS.Craig Topper
2017-12-15[SelectionDAG] Make getNode calls that take an ArrayRef of SDValue for operan...Craig Topper
2017-12-15[X86] Further rearrange the setOperationAction calls to separate the ones tha...Craig Topper
2017-12-15[X86] Group setOperationActions related to vXi1 masks together. NFCICraig Topper
2017-12-15[X86] Make ISD::INSERT_SUBVECTOR v8i1 legal with AVX512F because we should be...Craig Topper
2017-12-15[X86] Move some of the hasVLX qualified code out of the main hasAVX512 block ...Craig Topper
2017-12-15FastISel: support no-PLT PIC calls on ELF x86_64Saleem Abdulrasool
2017-12-15[WebAssembly] Implement @llvm.global_ctors and @llvm.global_dtorsSam Clegg
2017-12-14Remove a non-modular header (& inline it into its one use)David Blaikie
2017-12-14[AArch64] Test patchEvandro Menezes
2017-12-14EmitFuncArgumentDbgValue: Prefer stack slots over registers for stack argumentsAdrian Prantl
2017-12-14[X86] Remove an unnecessary SmallVector that was collecting chains for two SD...Craig Topper
2017-12-14TLI: Allow using PSV for intrinsic mem operandsMatt Arsenault
2017-12-14Fix many -Wsign-compare and -Wtautological-constant-compare warnings.Zachary Turner
2017-12-14[SimplifyCFG] don't sink common insts too soon (PR34603)Sanjay Patel
2017-12-14DAG: Expose all MMO flags in getTgtMemIntrinsicMatt Arsenault
2017-12-14[Hexagon] Generate HVX code for comparisons and selectsKrzysztof Parzyszek
2017-12-14[WebAssembly] Add support for init functions linking metadataSam Clegg
2017-12-14[SLPVectorizer] Don't ignore scalar extraction instructions of aggregate valueGuozhi Wei
2017-12-14Add MVT::v128i1, NFCKrzysztof Parzyszek
2017-12-14[MC] Allow .file directives to be out-of-orderPaul Robinson
2017-12-14[X86] Don't zero the upper bits of the k-register before extracting a single ...Craig Topper
2017-12-14[Hexagon] Remove vectors of i64 from valid HVX typesKrzysztof Parzyszek
2017-12-14[COFF] Teach LLD to use the COFF .debug$H section.Zachary Turner
2017-12-14[ARM] Fix isRenamable flag setting on expanded VSTMDIA opcode.Geoff Berry
2017-12-14Revert CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.valueYaxun Liu
2017-12-14Re-commit: [TableGen] AsmMatcher: Fix bug with reported diagnostic for operand.Sander de Smalen
2017-12-14[mips] Add partial support for R6 in the long branch passSimon Dardis
2017-12-14[ScalarEvolution] Fix base condition in isNormalAddRecPHI.Bjorn Pettersson
2017-12-14[InlineCost] Tracking Values through PHI NodesHaicheng Wu
2017-12-14Revert "[DAGCombine] Move AND nodes to multiple load leaves"Benjamin Kramer
2017-12-14Any Target Asm comments should start from MachineInstr::TAsmComments value.Andrew V. Tischenko
2017-12-14[AVX512] Adding support for load truncate store of I1Michael Zuckerman
2017-12-14[PM][InstCombine] fixing omission of AliasAnalysis in new-pass-manager's vers...Fedor Sergeev
2017-12-14Remove redundant includes from lib/Target/AArch64.Fedor Sergeev
2017-12-14[CodeGen] Print MCSymbol operands as <mcsymbol sym> in both MIR and debug outputFrancis Visoiu Mistrih
2017-12-14[CodeGen] Move printing MO_Metadata operands to MachineOperand::printFrancis Visoiu Mistrih
2017-12-14[CodeGen] Print live-out register lists as liveout(...) in both MIR and debug...Francis Visoiu Mistrih
2017-12-14[CodeGen] Print global addresses as @foo in both MIR and debug outputFrancis Visoiu Mistrih
2017-12-14[CodeGen] Print external symbols as $symbol in both MIR and debug outputFrancis Visoiu Mistrih
2017-12-14[Verifier] Check that GEP indexes has correct typesIgor Laevsky
2017-12-14[DAGCombine] Move AND nodes to multiple load leavesSam Parker
2017-12-14[X86] Make ANY_EXTEND from vXi1 Custom for more types.Craig Topper
2017-12-14[SelectionDAG][X86] Improve legalization of v32i1 CONCAT_VECTORS of v16i1 for...Craig Topper
2017-12-14[X86] Remove redundant setOperationAction calls.Craig Topper
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