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AgeCommit message (Expand)Author
2017-11-27[X86] Remove lines that set v8f32 FP_ROUND/FP_EXTEND to Legal under AVX512. NFCICraig Topper
2017-11-27[PartiallyInlineLibCalls][x86] add TTI hook to allow sqrt inlining to depend ...Sanjay Patel
2017-11-27[PowerPC] Remove redundant TOC savesZaara Syeda
2017-11-27[X86] Remove an unused isel pattern that looked for pshufd with v4f32 type.Craig Topper
2017-11-27[X86] Teach combineX86ShuffleChain that AllowIntDomain requires at least SSE2.Craig Topper
2017-11-27[X86][AVX512] Tag AVX512 PACKSS/PACKUS/PMADDWD/PMADDUBSW instructions with SS...Simon Pilgrim
2017-11-27[Hexagon] Implement HexagonSubtarget::isHVXVectorTypeKrzysztof Parzyszek
2017-11-27[X86] Make getSetCCResultType return vXi1 for any vXi32/vXi64 vector over 512...Craig Topper
2017-11-27[X86][SSE] Fix roundpd instructions to correctly use IIC_SSE_ROUNDPD_* itiner...Simon Pilgrim
2017-11-27[AMDGPU][MC][DISASSEMBLER][GFX9] Corrected decoding of GLOBAL/SCRATCH opcodesDmitry Preobrazhensky
2017-11-27[Power9] Improvements to vector extract with variable index exploitationZaara Syeda
2017-11-27[X86][AVX512] Tag AVX512 sqrt instructions with SSE_SQRT schedule classesSimon Pilgrim
2017-11-27[DAG] Do MergeConsecutiveStores again before Instruction SelectionNirav Dave
2017-11-27[X86] Add INVLPGA to the existing INVLPG schedulingSimon Pilgrim
2017-11-27[mips] fix asmstring of Ext and Ins instructions and mips16 JALRC/JRCPetar Jovanovic
2017-11-27[AMDGPU] Add custom lowering for llvm.log{,10}.{f16,f32} intrinsicsVedran Miletic
2017-11-27[X86][FMA] Tag all FMA/FMA4 instructions with WriteFMA schedule classSimon Pilgrim
2017-11-27[ARM] Fix an off-by-one error when restoring LR for 16-bit ThumbMomchil Velikov
2017-11-27Update BTVER2 sched numbers for SSE42 string instructions.Andrew V. Tischenko
2017-11-26[X86] Fix an assert that was incorrectly checking for BMI instead of AVX512VBMI.Craig Topper
2017-11-26[X86][3DNow] Add 3DNow! instruction itinerary and scheduling classesSimon Pilgrim
2017-11-26[X86][3DNow] Remove unused I3DNow_binop_rm/I3DNow_conv_rm templates. NFCISimon Pilgrim
2017-11-26[X86][MMX] Add IIC_MMX_MOVMSK instruction itinerary classSimon Pilgrim
2017-11-26Control-Flow Enforcement Technology - Shadow Stack support (LLVM side)Oren Ben Simhon
2017-11-26[x86][icelake]GFNICoby Tayree
2017-11-25[X86] Add separate intrinsics for scalar FMA4 instructions.Craig Topper
2017-11-25[X86] Don't report gather is legal on Skylake CPUs when AVX2/AVX512 is disabl...Craig Topper
2017-11-25Add BTVER2 sched support for SHLD/SHRD.Andrew V. Tischenko
2017-11-25[X86] Simplify some code in combineSetCC. NFCICraig Topper
2017-11-25[X86] Qualify some vector specific code with VT.isVector(). NFCICraig Topper
2017-11-25[X86] Support folding to andnps with SSE1 only.Craig Topper
2017-11-25[X86] Add some early DAG combines to turn v4i32 AND/OR/XOR into FAND/FOR/FXOR...Craig Topper
2017-11-24[X86] Prevent using X * rsqrt(X) to approximate sqrt when only sse1 is enabled.Craig Topper
2017-11-24[AMDGPU][MC][GFX9] Added v_interp_p2_f16 and v_interp_p2_legacy_f16Dmitry Preobrazhensky
2017-11-24Make helpers static. NFC.Benjamin Kramer
2017-11-24[mips] Set microMIPS ASE flagAleksandar Beserminji
2017-11-24[AMDGPU][MC][GFX9] Added support of 'inst_offset' modifier for compatibility ...Dmitry Preobrazhensky
2017-11-23[X86] Don't invert NewCC variable while processing the jcc/setcc/cmovcc instr...Craig Topper
2017-11-23[X86] Teach isel that X86ISD::CMPM_RND zeros the upper bits of the mask regis...Craig Topper
2017-11-23[X86] Remove some unneeded opcodes from getVectorMaskingNode. NFCCraig Topper
2017-11-23[X86] Add X86ISD::CMPM_RND to getVectorMaskingNode to select ISD::AND instead...Craig Topper
2017-11-23[X86] Remove some dead code leftover from when i1 was a legal type. NFCICraig Topper
2017-11-23[X86] Remove some dead code. NFCCraig Topper
2017-11-23[X86][SSE] Use (V)PHMINPOSUW for vXi16 SMAX/SMIN/UMAX/UMIN horizontal reducti...Simon Pilgrim
2017-11-23[ARM GlobalISel] Support G_FDIV for s32 and s64Diana Picus
2017-11-23[ARM GlobalISel] Support G_FMUL for s32 and s64Diana Picus
2017-11-23[mips] Use the delay slot filler to convert branches for microMIPSR6.Simon Dardis
2017-11-23[x86][icelake]BITALGCoby Tayree
2017-11-23Add backend name to AVR Target to enable runtime info to be fed back into Tab...Leslie Zhai
2017-11-23[X86] Turn an if condition that should always be true into an assert. NFCICraig Topper
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