index
:
ampere-computing/llvm.git
release_60-f1b37feef3d-amp-20180630
release_70-e8af9b4c407-amp-20181130
LLVM including Ampere Computing toolchain specific patches
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
lib
/
Target
Age
Commit message (
Expand
)
Author
2018-02-02
Merging r323908:
Hans Wennborg
2018-02-02
Merging r323643:
Hans Wennborg
2018-02-02
Merging r323909:
Hans Wennborg
2018-02-02
Merging r323536:
Hans Wennborg
2018-02-02
Merging r323781:
Hans Wennborg
2018-02-02
Merging r323857:
Hans Wennborg
2018-02-02
Merging r323915:
Hans Wennborg
2018-02-02
Merging r323155:
Hans Wennborg
2018-01-31
Merging r323810:
Hans Wennborg
2018-01-30
Merging r323706:
Hans Wennborg
2018-01-30
Merging r323469:
Hans Wennborg
2018-01-30
Merging r323672: (test-case re-generated)
Hans Wennborg
2018-01-25
Merging r323369 and r323371:
Hans Wennborg
2018-01-24
Merging r323190:
Hans Wennborg
2018-01-24
Merging r322372 and r322767:
Hans Wennborg
2018-01-22
Merging r322878:
Hans Wennborg
2018-01-19
Merging r322053:
Hans Wennborg
2018-01-18
Merging r322644:
Hans Wennborg
2018-01-18
Merging r322724:
Hans Wennborg
2018-01-17
Merging r322106:
Hans Wennborg
2018-01-17
Merging r322272:
Hans Wennborg
2018-01-17
Merging r322623:
Hans Wennborg
2018-01-03
Remove left-over debug printout from r321692
Hans Wennborg
2018-01-03
[ARM][NFC] Avoid recreating MCSubtargetInfo in ARMAsmBackend
Alex Bradbury
2018-01-03
[AArch64][SVE] Asm: Add restricted register classes for SVE predicate vectors.
Sander de Smalen
2018-01-03
Fix build of WebAssembly and AVR backends after r321692
Alex Bradbury
2018-01-03
Thread MCSubtargetInfo through Target::createMCAsmBackend
Alex Bradbury
2018-01-02
Handle the case of live 16-bit subregisters in X86FixupBWInsts
Andrew Kaylor
2018-01-02
[x86] allow pairs of PCMPEQ for vector-sized integer equality comparisons (PR...
Sanjay Patel
2018-01-02
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
Amara Emerson
2018-01-02
[Hexagon] Fix generation of vector sign extensions
Krzysztof Parzyszek
2018-01-02
[AArch64][AsmParser] Add isScalarReg() and repurpose isReg()
Sander de Smalen
2018-01-02
Strip trailing whitespace. NFCI
Simon Pilgrim
2018-01-02
[RISCV] Add Defs Uses information for c.jal and c.addi4spn
Alex Bradbury
2018-01-02
[RISCV][NFC] Resolve unused variable warning in RISCVISelLowering
Alex Bradbury
2018-01-01
[X86] Promote vXi1 fp_to_uint/fp_to_sint to vXi32 to avoid scalarization.
Craig Topper
2018-01-01
[X86] Replace custom lowering of vXi1 SINT_TO_FP/UINT_TO_FP with promotion.
Craig Topper
2018-01-01
[SelectionDAG][X86][AArch64] Require targets to specify the promotion type wh...
Craig Topper
2018-01-01
[X86] In LowerTruncateVecI1, don't add SHL if the input is known to be all si...
Craig Topper
2018-01-01
[X86] Add missing NoVLX predicate around some patterns that use zmm registers...
Craig Topper
2018-01-01
[X86] Add patterns for using zmm registers for v8i32/v8f32 vselect with the f...
Craig Topper
2017-12-31
[X86] Use CONCAT_VECTORS instead of INSERT_SUBVECTOR for padding v4i1/v2i1 ve...
Craig Topper
2017-12-31
[X86][AVX2] Combine extract(broadcast(scalar_value)) --> scalar_value
Simon Pilgrim
2017-12-31
[X86][SSE] Don't vectorize splat buildvector of binops (PR30780)
Simon Pilgrim
2017-12-31
[X86] Add a DAG combine to widen (i4 (bitcast (v4i1))) before type legalizati...
Craig Topper
2017-12-31
[X86] Add a DAG combine to fix (v4i1 (bitcast (i4))) before type legalization...
Craig Topper
2017-12-31
[X86] Prevent combining (v8i1 (bitconvert (i8 load)))->(v8i1 load) if we don'...
Craig Topper
2017-12-31
[X86] Remove patterns for load/store of vXi with bitcasts to/from integer.
Craig Topper
2017-12-31
[X86] Remove AND32ri8 from pattern for v1i1 load.
Craig Topper
2017-12-31
[X86] Fix a crash when returning a <1 x i1> value>
Craig Topper
[next]