| Age | Commit message (Expand) | Author |
|---|
| 2017-12-15 | [X86] Add 'Requires<[In64BitMode]>' to a bunch of instructions that only have... | Craig Topper |
| 2017-12-15 | [X86] Remove the 'Requires<[In64BitMode]>' from SHSTK instructions. | Craig Topper |
| 2017-12-15 | [X86] Fix XSAVE64 and similar instructions to not be allowed by the assembler... | Craig Topper |
| 2017-12-13 | [X86] Add RDMSR/WRMSR, RDPMC + RDTSC/RDTSCP schedule tests | Simon Pilgrim |
| 2017-12-09 | Strip trailing whitespace. NFCI. | Simon Pilgrim |
| 2017-12-09 | [X86] Tag FS/GS BASE R/W instruction scheduler classes | Simon Pilgrim |
| 2017-12-09 | [X86] Tag segment prefixes as NOP instruction scheduling classes | Simon Pilgrim |
| 2017-12-08 | [X86] Tag VIA PadLock crypto instructions scheduler classes | Simon Pilgrim |
| 2017-12-08 | [X86] Tag PKU/INVPCID/RDPID/SMAP/SMX/PTWRITE system instructions scheduler cl... | Simon Pilgrim |
| 2017-11-26 | Control-Flow Enforcement Technology - Shadow Stack support (LLVM side) | Oren Ben Simhon |
| 2017-11-21 | Avoid unecessary opsize byte in segment move to memory | Nirav Dave |
| 2017-11-21 | Revert r318678 to fix Clang test | Richard Trieu |
| 2017-11-20 | [X86] Avoid unecessary opsize byte in segment move to memory | Nirav Dave |
| 2017-10-23 | [X86] Change XRSTOR to use PS instead of TB to match XSAVE. | Craig Topper |
| 2017-10-23 | [X86] Add PTWRITE instruction for assembler and disassembler. | Craig Topper |
| 2017-10-23 | [X86] Add RDPID instruction for assembler and disassembler. | Craig Topper |
| 2017-09-20 | 'into' instruction should not be decoded as a valid instr in 64-bit mode | Andrew V. Tischenko |
| 2017-04-13 | [X86] Added missing mayLoad/mayStore attributes to some X86 instructions. | Ayman Musa |
| 2016-08-16 | [X86] Add xgetbv/xsetbv intrinsics to non-windows platforms | Guy Blank |
| 2016-08-09 | [X86] Don't model UD2/UD2B as a terminator | David Majnemer |
| 2016-06-18 | test commit: remove trailing whitespace | Zvi Rackover |
| 2016-03-13 | [X86] Remove many operands that represent memory stores from outs to ins. The... | Craig Topper |
| 2016-01-26 | [X86] Mark LDS/LES as not being allowed in 64-bit mode. | Craig Topper |
| 2016-01-06 | [X86] Use PS instead of TB for instructions that have PD/XS/XD variations. Us... | Craig Topper |
| 2015-12-31 | [X86][PKU] Add {RD,WR}PKRU intrinsics | Asaf Badouh |
| 2015-12-24 | [X86][PKU] Add {RD,WR}PKRU encoding | Asaf Badouh |
| 2015-12-21 | Implemented Support of IA interrupt and exception handlers: | Amjad Aboud |
| 2015-10-12 | [X86] Add XSAVE intrinsic family | Amjad Aboud |
| 2015-10-12 | [X86] Change the immediate for IN/OUT instructions to u8imm so the assembly p... | Craig Topper |
| 2015-10-11 | [X86] Remove special validation for INT immediate operand from AsmParser. Ins... | Craig Topper |
| 2015-02-07 | [X86] Add register use/def for wrmsr and rdmsr. | Craig Topper |
| 2015-02-07 | [X86] Add GETSEC instruction. | Craig Topper |
| 2015-02-05 | [X86] Add xrstors/xsavec/xsaves/clflushopt/clwb/pcommit instructions | Craig Topper |
| 2015-02-05 | [X86] Remove two feature flags that covered sets of instructions that have no... | Craig Topper |
| 2015-02-03 | [X86] Make fxsave64/fxrstor64/xsave64/xsrstor64/xsaveopt64 parseable in AT&T ... | Craig Topper |
| 2015-01-26 | Use a different encoding for debugtrap on PS4. | Alex Rosenberg |
| 2014-12-04 | [X86] Clean up whitespace as well as minor coding style | Michael Liao |
| 2014-09-04 | X86: cpuid and xgetbv write to 32-bit registers, not 64-bit | Reid Kleckner |
| 2014-08-21 | [x86] SMAP: added HasSMAP attribute for CLAC/STAC, corrected attributes | Robert Khasanov |
| 2014-06-30 | [X86] Add support for builtin to read performance monitoring counters. | Andrea Di Biagio |
| 2014-04-24 | [X86] Add support for Read Time Stamp Counter x86 builtin intrinsics. | Andrea Di Biagio |
| 2014-02-27 | [X86] Fix Uses/Defs lists for INS, OUTS, SCAS, CMPS, LODS | Craig Topper |
| 2014-02-26 | [x86] Add same itinerary to SYSEXIT64 as SYSEXIT for consistency. | Craig Topper |
| 2014-02-19 | Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0x... | Craig Topper |
| 2014-02-18 | Add a bunch of OpSize32 tags to 64-bit mode only instructions to match their ... | Craig Topper |
| 2014-02-02 | Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 ... | Craig Topper |
| 2014-02-01 | Simplify some x86 format classes and remove some ambiguities in their applica... | Craig Topper |
| 2014-01-28 | x86: add implicit defs for cpuid | Reid Kleckner |
| 2014-01-22 | [x86] Allow segment and address-size overrides for INS[BWLQ] (PR9385) | David Woodhouse |
| 2014-01-17 | Switch a few instructions to use RI instead I so they don't require REX_W to ... | Craig Topper |
