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2017-10-02Add support for Myriad ma2x8x series of CPUsWalter Lee
Summary: Also add support for some older Myriad CPUs that were missing. Reviewers: jyknight Subscribers: fedor.sergeev Differential Revision: https://reviews.llvm.org/D37552 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314705 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-20[SPARC] Clean up the support for disabling fsmuld and fmuls instructions.James Y Knight
Summary: Also enable no-fsmuld for sparcv7 (which doesn't have the instruction). The previous code which used a post-processing pass to do this was unnecessary; disabling the instruction is entirely sufficient. Reviewers: jacob_hansen, ekedaigle Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D35576 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308661 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-18[Sparc] Added software multiplication/division featureJames Y Knight
Added a feature to the Sparc back-end that replaces the integer multiply and divide instructions with calls to .mul/.sdiv/.udiv. This is a step towards having full v7 support. Patch by: Eric Kedaigle Differential Revision: https://reviews.llvm.org/D35500 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308343 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-10This pass, fixing an erratum in some LEON 2 processors ensures that the SDIV ↵Chris Dewhurst
instruction is not issued, but replaced by SDIVcc instead, which does not exhibit the error. Unit test included. Differential Review: https://reviews.llvm.org/D24660 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283727 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-13[Myriad]: set LeonCASA processor featureDouglas Katzman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281359 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-29[Myriad]: add missing 'mcpu' valuesDouglas Katzman
Should have been done with r276646. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279996 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-12Revert "[Sparc] Leon errata fix passes."James Y Knight
...and the two followup commits: Revert "[Sparc][Leon] Missed resetting option flags from check-in 278489." Revert "[Sparc][Leon] Errata fixes for various errata in different versions of the Leon variants of the Sparc 32 bit processor." This reverts commit r274856, r278489, and r278492. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278511 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-12[Sparc][Leon] Errata fixes for various errata in different versions of the ↵Chris Dewhurst
Leon variants of the Sparc 32 bit processor. The nature of the errata are listed in the comments preceding the errata fix passes. Relevant unit tests are implemented for each of these. These changes update older versions of these errata fixes with improvements to code and unit tests. Differential Revision: https://reviews.llvm.org/D21960 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278489 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-08[Sparc] Leon errata fix passes.Chris Dewhurst
Errata fixes for various errata in different versions of the Leon variants of the Sparc 32 bit processor. The nature of the errata are listed in the comments preceding the errata fix passes. Relevant unit tests are implemented for each of these. Note: Running clang-format has changed a few other lines too, unrelated to the implemented errata fixes. These have been left in as this keeps the code formatting consistent. Differential Revision: http://reviews.llvm.org/D21960 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274856 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-19[SPARC] Fixes for hardware errata on LEON processor.Chris Dewhurst
Passes to fix three hardware errata that appear on some LEON processor variants. The instructions FSMULD, FMULS and FDIVS do not work as expected on some LEON processors. This change allows those instructions to be substituted for alternatives instruction sequences that are known to work. These passes only run when selected individually, or as part of a processor defintion. They are not included in general SPARC processor compilations for non-LEON processors or for those LEON processors that do not have these hardware errata. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273108 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-23[Sparc][LEON] LEON Erratum fix. Insert NOP after LD or LDF instruction.Chris Dewhurst
Due to an erratum in some versions of LEON, we must insert a NOP after any LD or LDF instruction to ensure the processor has time to load the value correctly before using it. This pass will implement that erratum fix. The code will have no effect for other Sparc, but non-LEON processors. Differential Review: http://reviews.llvm.org/D20353 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@270417 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-18[Sparc] Add Soft Float supportChris Dewhurst
This change adds support for software floating point operations for Sparc targets. This is the first in a set of patches to enable software floating point on Sparc. The next patch will enable the option to be used with Clang. Differential Revision: http://reviews.llvm.org/D19265 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269892 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-16[Sparc][LEON] Add LEON-specific CASA instruction.Chris Dewhurst
Differental Revision: http://reviews.llvm.org/D20098 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269644 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09[Sparc][LEON] Add UMAC and SMAC instruction support for Sparc LEON subtargetsChris Dewhurst
This change adds SMAC (signed multiply-accumulate) and UMAC (unsigned multiply-accumulate) for LEON subtargets of the Sparc processor. The new files LeonFeatures.td and leon-instructions.ll will both be expanded in future, so I want to leave them separate as small files for this review, to be expanded in future check-ins. Note: The functions are provided only for inline-assembly provision. No DAG selection is provided. Differential Revision: http://reviews.llvm.org/D19911 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268908 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22[Sparc] This provides support for itineraries on Sparc.Chris Dewhurst
Specifically, itineraries for LEON processors has been added, along with several LEON processor Subtargets. Although currently all these targets are pretty much identical, support for features that will differ among these processors will be added in the very near future. The different Instruction Itinerary Classes (IICs) added are sufficient to differentiate between the instruction timings used by LEON and, quite probably, by generic Sparc processors too, but the focus of the exercise has been for LEON processors, as the requirement of my project. If the IICs are not sufficient for other Sparc processor types and you want to add a new itinerary for one of those, it should be relatively trivial to adapt this. As none of the LEON processors has Quad Floats, or is a Version 9 processor, none of those instructions have itinerary classes defined and revert to the default "NoItinerary" instruction itinerary. Phabricator Review: http://reviews.llvm.org/D19359 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267121 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-15Myriad: Add new sparc CPU kinds.Douglas Katzman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263557 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-28[SparcInstPrinter] Use the subtarget that is passed to the print functionAkira Hatanaka
instead of the one passed to the constructor. Unfortunately, I don't have a test case for this change. In order to test my change, I will have to run the code after line 90 in printSparcAliasInstr. I couldn't make that happen because printAliasInstr would always handle the printing of fcmp instructions that the code after line 90 is supposed to handle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233471 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-02[Sparc] Add VIS instructions to sparc backend.Venkatraman Govindaraju
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202660 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-26Only generate the popc instruction for SPARC CPUs that implement it.Jakob Stoklund Olesen
The popc instruction is defined in the SPARCv9 instruction set architecture, but it was emulated on CPUs older than Niagara 2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200131 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-11[Sparc] Add missing processor types: v7 and niagaraVenkatraman Govindaraju
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199024 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-04[Sparc] Add the initial implementation of an asm parser for sparc/sparcv9.Venkatraman Govindaraju
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198484 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-26[Sparc] Lower and MachineInstr to MC and print assembly using MCInstPrinter.Venkatraman Govindaraju
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198030 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-02Change the default of AsmWriterClassName and isMCAsmWriter.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196065 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-25[Sparc] Add long double (f128) instructions to sparc backend. Venkatraman Govindaraju
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189198 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04Sparc: No functionality change. Cleanup whitespaces, comment formatting etc.,Venkatraman Govindaraju
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183243 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-18Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu
MSP430, PPC, PTX, Sparc, X86, XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17fix emacs language spec's, patch by Edmund Grimley-Evans!Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111241 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-05Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.Jakob Stoklund Olesen
When a target instruction wants to set target-specific flags, it should simply set bits in the TSFlags bit vector defined in the Instruction TableGen class. This works well because TableGen resolves member references late: class I : Instruction { AddrMode AM = AddrModeNone; let TSFlags{3-0} = AM.Value; } let AM = AddrMode4 in def ADD : I; TSFlags gets the expected bits from AddrMode4 in this example. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100384 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-24Move target independent td files from lib/Target/ to include/llvm/Target so ↵Evan Cheng
they can be distributed along with the header files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59953 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-17Start moving sparc to use SparcCallingConv.td, switching overChris Lattner
return lowering first. This fixes a bug where the top and bottom of i64 values were returned in the wrong registers before. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48443 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-29Remove attribution from file headers, per discussion on llvmdev.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-18getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28378 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-17Remove PointerType from class TargetEvan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28368 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-05Rename SPARC V8 target to be the LLVM SPARC target.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25985 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-27Subtarget feature can now set any variable to any valueEvan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25678 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-27PHI and INLINEASM are now built-in instructions provided by Target.tdChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25674 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-26Rest of subtarget support, remove references to ppcChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25642 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-26Add trivial subtarget supportChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25641 91177308-0d34-0410-b5e6-96231b3b80d8
2004-12-10Adjust paths: Sparc/V8 --> SparcV8Brian Gaeke
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18737 91177308-0d34-0410-b5e6-96231b3b80d8
2004-09-22Prettify formatting of the file, adjust paths to making V8 a subdir of SparcMisha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16482 91177308-0d34-0410-b5e6-96231b3b80d8
2004-04-06Delete reference to "the Mach-O Runtime ABI".Brian Gaeke
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12726 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-28Tab completion is our friend.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11957 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-25Clean up the tablegen descriptions for SparcV8.Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11834 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-25SparcV8 skeletonBrian Gaeke
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11828 91177308-0d34-0410-b5e6-96231b3b80d8
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