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path: root/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
AgeCommit message (Expand)Author
2018-06-27[RISCV] Add machine function pass to merge base + offsetSameer AbuAsal
2018-05-29[RISCV] Add peepholes for Global Address lowering patternsSameer AbuAsal
2018-05-14Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen
2018-05-05Fix a bunch of places where operator-> was used directly on the return from d...Craig Topper
2018-04-18Revert "[RISCV] implement li pseudo instruction"Alex Bradbury
2018-04-17[RISCV] implement li pseudo instructionAlex Bradbury
2018-04-12[RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling ...Alex Bradbury
2018-03-19[RISCV] Peephole optimisation for load/store of global values or constant add...Alex Bradbury
2018-01-26[SelectionDAGISel] Add a debug print before call to Select. Adjust where blan...Craig Topper
2018-01-10[RISCV] Add basic support for inline asm constraintsAlex Bradbury
2017-12-11[RISCV] Support lowering FrameIndexAlex Bradbury
2017-11-21[RISCV][NFC] Clean up RISCVDAGToDAGISel::SelectAlex Bradbury
2017-11-21[RISCV] Use register X0 (ZERO) for constant 0Alex Bradbury
2017-10-19[RISCV] Initial codegen support for ALU operationsAlex Bradbury
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