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path: root/lib/Target/RISCV/RISCV.td
AgeCommit message (Expand)Author
2018-05-15[RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxa...Shiva Chen
2018-02-23[MachineOperand][Target] MachineOperand::isRenamable semantics changesGeoff Berry
2018-01-12[RISCV] Pass MCSubtargetInfo to print methods.Ana Pazos
2017-12-12[RISCV] Implement assembler pseudo instructions for RV32I and RV64IAlex Bradbury
2017-12-07[RISCV] MC layer support for load/store instructions of the C (compressed) ex...Alex Bradbury
2017-12-07[RISCV] MC layer support for the standard RV64I instructionsAlex Bradbury
2017-12-07[RISCV] MC layer support for the standard RV32D instruction set extensionAlex Bradbury
2017-12-07[RISCV] MC layer support for the standard RV32F instruction set extensionAlex Bradbury
2017-11-09[RISCV] MC layer support for the standard RV32A instruction set extensionAlex Bradbury
2017-11-09[RISCV] MC layer support for the standard RV32M instruction set extensionAlex Bradbury
2017-11-08[NFCI] Ensure TargetOpcode::* are compatible with guessInstructionProperties=0Alex Bradbury
2017-10-19[RISCV] Add missing hunk from r316188Alex Bradbury
2017-10-19[RISCV] Initial codegen support for ALU operationsAlex Bradbury
2017-10-19[RISCV] Prepare for the use of variable-sized register classesAlex Bradbury
2017-08-08[RISCV] Add basic RISCVAsmParserAlex Bradbury
2016-11-01[RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.tdAlex Bradbury
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