| Age | Commit message (Expand) | Author |
|---|---|---|
| 2016-04-26 | Remove MinLatency in SchedMachineModel. NFC. | Junmo Park |
| 2016-03-01 | TableGen: Check scheduling models for completeness | Matthias Braun |
| 2015-07-14 | [PowerPC] Fix the PPCInstrInfo::getInstrLatency implementation | Hal Finkel |
| 2015-02-01 | [PowerPC] Better scheduling for isel on P7/P8 | Hal Finkel |
| 2015-01-10 | [PowerPC] Readjust the loop unrolling threshold | Hal Finkel |
| 2015-01-09 | [PowerPC] Enable late partial unrolling on the POWER7 | Hal Finkel |
| 2014-03-31 | [PowerPC] Correct P7 dispatch unit allocation for vector instructions | Hal Finkel |
| 2014-03-29 | [PowerPC] VSX instruction latency corrections | Hal Finkel |
| 2014-01-02 | [PPC] Fix the scheduling of CR logicals on the P7 | Hal Finkel |
| 2013-12-12 | Improve instruction scheduling for the PPC POWER7 | Hal Finkel |
| 2013-11-30 | Add a scheduling model (with itinerary) for the PPC POWER7 | Hal Finkel |
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index : ampere-computing/llvm.git | |
| LLVM including Ampere Computing toolchain specific patches |
| summaryrefslogtreecommitdiff |