| Age | Commit message (Expand) | Author |
|---|---|---|
| 2017-02-23 | [NVPTX] Added support for .f16x2 instructions. | Artem Belevich |
| 2017-01-13 | [NVPTX] Added support for half-precision floating point. | Artem Belevich |
| 2015-06-24 | Add NVPTXPeephole pass to reduce unnecessary address cast | Jingyue Wu |
| 2014-07-16 | [NVPTX] Rename registers %fl -> %fd and %rl -> %rd | Justin Holewinski |
| 2014-06-27 | [NVPTX] Add support for envreg reads | Justin Holewinski |
| 2013-07-01 | [NVPTX] Cut down on physical register defs | Justin Holewinski |
| 2013-06-28 | [NVPTX] Remove i8 register class. PTX support for i8 (.b8, .u8, .s8) is rath... | Justin Holewinski |
| 2013-02-12 | [NVPTX] Disable vector registers | Justin Holewinski |
| 2012-05-24 | Shrink. | Jakob Stoklund Olesen |
| 2012-05-04 | This patch adds a new NVPTX back-end to LLVM which supports code generation f... | Justin Holewinski |
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index : ampere-computing/llvm.git | |
| LLVM including Ampere Computing toolchain specific patches |
| summaryrefslogtreecommitdiff |