Age | Commit message (Expand) | Author |
2017-12-11 | [Hexagon] Add support for Hexagon V65 | Krzysztof Parzyszek |
2017-09-15 | [Hexagon] Switch to parameterized register classes for HVX | Krzysztof Parzyszek |
2017-09-14 | [Hexagon] Make getMemAccessSize return size in bytes | Krzysztof Parzyszek |
2017-05-03 | [Hexagon] Use automatically-generated scheduling information for HVX | Krzysztof Parzyszek |
2017-05-02 | [Hexagon] Remove unused validSubtarget TSFlags | Krzysztof Parzyszek |
2017-05-01 | [Hexagon] Replace CVI_VM_CUR_LD type with CVI_VM_LD | Krzysztof Parzyszek |
2017-02-10 | [Hexagon] Replace instruction definitions with auto-generated ones | Krzysztof Parzyszek |
2017-02-07 | [Hexagon] Update instruction types | Krzysztof Parzyszek |
2017-02-06 | [Hexagon] Update MCTargetDesc | Krzysztof Parzyszek |
2016-11-17 | Fix spelling mistakes in Hexagon target comments. NFC. | Simon Pilgrim |
2016-10-08 | [Hexagon] Adding change of flow max 1 (cofMax1) TS flag for marking this rest... | Colin LeMahieu |
2016-07-15 | [Hexagon] Update instruction itineraries | Krzysztof Parzyszek |
2015-10-20 | [Hexagon] Remove the remnants of isConstExtProfitable | Krzysztof Parzyszek |
2015-10-17 | [Hexagon] Adding skeleton of HVX extension instructions. | Colin LeMahieu |
2015-05-29 | [Hexagon] Disassembling, printing, and emitting instructions a whole-bundle a... | Colin LeMahieu |
2015-03-10 | [Hexagon] Separating InstHexagon from OpcodeHexagon. | Colin LeMahieu |
2015-02-09 | [Hexagon] Removing v2-4 flags. V4 is the minimum supported version. | Colin LeMahieu |
2015-02-05 | [Hexagon] Since decoding conflicts have been resolved, isCodeGenOnly = 0 by d... | Colin LeMahieu |
2015-02-04 | [Hexagon] Revert change to isCodeGenOnly = 1 in r228080 | Colin LeMahieu |
2015-02-04 | [Hexagon] Changing some isCodeGenOnly to isAsmParserOnly since we want them t... | Colin LeMahieu |
2014-12-23 | [Hexagon] Reapplying 224775 load words. | Colin LeMahieu |
2014-12-10 | [Hexagon] Adding encodings for JR class instructions. Updating complier usages. | Colin LeMahieu |
2014-10-22 | [Hexagon] Adding basic disassembler. | Colin LeMahieu |
2014-05-08 | [Hexagon] Add new InstrItinClass to support timing classes. | Jyotsna Verma |
2014-05-07 | [Hexagon] Add New TSFlags to be used in the upcoming patches. | Jyotsna Verma |
2013-09-28 | Even more spelling fixes for "instruction". | Robert Wilhelm |
2013-05-10 | Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp. | Jyotsna Verma |
2013-05-07 | Hexagon: Set accessSize and addrMode on all load/store instructions. | Jyotsna Verma |
2013-02-14 | Hexagon: Change insn class to support instruction encoding. | Jyotsna Verma |
2012-11-14 | Added multiclass for post-increment load instructions. | Jyotsna Verma |
2012-11-01 | Use the relationship models infrastructure to add two relations - getPredOpcode | Pranav Bhandarkar |
2012-05-10 | Hexagon V5 FP Support. | Sirish Pande |
2012-05-03 | Extensions of Hexagon V4 instructions. | Sirish Pande |
2012-04-23 | Revert r155365, r155366, and r155367. All three of these have regression | Chandler Carruth |
2012-04-23 | Hexagon V5 (floating point) support. | Sirish Pande |
2012-04-23 | Support for Hexagon VLIW Packetizer. | Sirish Pande |
2012-04-18 | This reverts a long string of commits to the Hexagon backend. These | Chandler Carruth |
2012-04-16 | Hexagon V5 (Floating Point) Support. | Sirish Pande |
2012-04-12 | HexagonPacketizer patch. | Sirish Pande |
2012-02-18 | Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,... | Jia Liu |
2012-02-08 | Use TSFlag bit to describe instruction properties. | Brendon Cahoon |
2011-12-12 | Hexagon backend support | Tony Linthicum |