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path: root/lib/Target/ARM/ARMScheduleV6.td
AgeCommit message (Expand)Author
2014-04-03Tidy up. Trailing whitespace.Jim Grosbach
2012-04-11Fix a number of problems with ARM fused multiply add/subtract instructions.Evan Cheng
2012-02-18Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,...Jia Liu
2011-01-20Sorry, several patches in one.Evan Cheng
2010-11-13Conditional moves are slightly more expensive than moves.Evan Cheng
2010-10-21putback r116983 and fix simple-fp-encoding.ll testsAndrew Trick
2010-10-21Revert r116983, which is breaking all the buildbots.Owen Anderson
2010-10-21Add missing scheduling itineraries for transfers between core registers and V...Evan Cheng
2010-10-07Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vld...Evan Cheng
2010-10-06- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. ThisEvan Cheng
2010-09-30ARM instruction itinerary fixes:Evan Cheng
2010-09-29Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn.Evan Cheng
2010-09-29Assign bitwise binary instructions different itinerary classes from ALU instr...Evan Cheng
2010-09-28Add support to model pipeline bypass / forwarding.Evan Cheng
2010-09-25Remove a unused instruction itinerary class.Evan Cheng
2010-09-25Fix zero and sign extension instructions scheduling itineraries.Evan Cheng
2010-09-24More pseudo instruction scheduling itinerary fixes.Evan Cheng
2010-09-09For each instruction itinerary class, specify the number of micro-ops eachEvan Cheng
2010-06-02Clean up 80 column violations. No functional change.Jim Grosbach
2010-04-18Make processor FUs unique for given itinerary. This extends the limit of 32Anton Korobeynikov
2009-11-18Add ARMv6 itineraries.David Goodwin
2009-09-23Checkpoint NEON scheduling itineraries.David Goodwin
2009-09-21Add Cortex-A8 VFP model.David Goodwin
2009-08-19Update Cortex-A8 instruction itineraries for integer instructions.David Goodwin
2009-08-15Turn on if-conversion for thumb2.Evan Cheng
2009-08-13Finalize itineraries for cortex-a8 integer multiplyDavid Goodwin
2009-08-11Allow a zero cycle stage to reserve/require a FU without advancing the cycle ...David Goodwin
2009-08-10Checkpoint scheduling itinerary changes.David Goodwin
2009-07-21Fix comment.Evan Cheng
2009-06-19Latency information for ARM v6. It's rough and not yet hooked up. Right now ...Evan Cheng